LAYOUT DESIGN METHOD AND LAYOUT DESIGN APPARATUS OF SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To eliminate clock buffers excessively inserted by clock tree synthesis (CTS) and to reduce power consumption of a semiconductor device.SOLUTION: A layout design method includes selecting, from a clock tree obtained by CTS: a clock line that has a fanout of a prescribed value o...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	SATO KAZUICHI, TERAUCHI YOSHIHIKO, SUGISAKI HIROKI, HATA NAOHIRO, KOIDE YUI, ANDO HIROYUKI, YAMAUCHI MANABU
Format:	Patent
Sprache:	eng ; jpn
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES
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