CIRCUIT AND METHOD FOR PACKET BAND CONTROL
PROBLEM TO BE SOLVED: To insert an invalid region so as to obtain a predetermined band in average.SOLUTION: A memory 101 is a first-in first-out memory which stores parallel data in which a packet is made into parallel. An output unit 102 reads out and outputs the parallel data stored in the memory...
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| Sprache: | eng ; jpn |
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| Zusammenfassung: | PROBLEM TO BE SOLVED: To insert an invalid region so as to obtain a predetermined band in average.SOLUTION: A memory 101 is a first-in first-out memory which stores parallel data in which a packet is made into parallel. An output unit 102 reads out and outputs the parallel data stored in the memory 101 with a predetermined bus width, and outputs an invalid region in a period when no parallel data is read out from the memory 101. A control unit 103 controls the readout and non-readout of the parallel data by the output unit 102 in such a manner that the packet band output from the output unit 102 becomes a predetermined band in average.SELECTED DRAWING: Figure 1
【課題】平均して所定の帯域となるように無効領域を挿入すること。【解決手段】メモリ１０１は、パケットがパラレル化されたパラレル化データを格納する先入れ先出しのメモリである。出力部１０２は、メモリ１０１に格納されたパラレル化データを所定のバス幅で読み出して出力し、メモリ１０１からパラレル化データを読み出さない期間においては無効領域を出力する。制御部１０３は、出力部１０２から出力されるパケットの帯域が平均して所定の帯域となるように出力部１０２によるパラレル化データの読み出しおよび非読み出しを制御する。【選択図】図１ |
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