SEMICONDUCTOR DEVICE MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which inhibits chip cracks and poor bump connection, and achieves improved yield and reliability.SOLUTION: A semiconductor device manufacturing method comprises the steps of: preparing a semiconductor wafer 101 where electr...

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Hauptverfasser: TAMAGAWA MICHIAKI, WATANABE SHINJI, KUMAGAI KINICHI, MATSUBARA HIROAKI, MIYAKOSHI TAKESHI, SAKUMOTO SHOTARO, NAKAMURA TAKU, DEMACHI HIROSHI, HOSOYAMADA SUMIKAZU, NAKAMURA SHINGO, CHIKAI TOMOYA, IWASAKI TOSHIHIRO, ISHIDO KIMINORI, HONDA HIROKAZU
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which inhibits chip cracks and poor bump connection, and achieves improved yield and reliability.SOLUTION: A semiconductor device manufacturing method comprises the steps of: preparing a semiconductor wafer 101 where electrodes are formed; electrically connecting first semiconductor elements 103 formed in semiconductor chips 105 and the electrodes of the semiconductor wafer via bumps 109; forming a first insulation resin layer 111 between the semiconductor wafer and the semiconductor chips; forming on the semiconductor wafer, a second insulation resin layer 113 to a thickness of embedding the semiconductor chips; grinding the second insulation resin layer and the semiconductor chips until reaching a predetermined thickness of the semiconductor chip; forming a first insulation layer 114 on the second insulation resin layer and the semiconductor chips; forming openings for exposing the electrode 104 in the insulation resin layer; forming wiring 117 and terminals 121 by a conductive material; grinding the semiconductor to a predetermined thickness; and subsequently dicing the semiconductor wafer along boundary lines of element regions.SELECTED DRAWING: Figure 8 【課題】チップクラック及びバンプ接続不良が抑制され、歩留まりと信頼性が向上された半導体装置の製造方法を提供する。【解決手段】電極が形成された半導体ウエハ101を準備し、半導体チップ105に形成された第一の半導体素子103と半導体ウエハの電極とをバンプ109を介して電気的に接続し、半導体ウエハと半導体チップとの間隙に第一の絶縁樹脂層111を形成し、半導体ウエハ上に、半導体チップが埋まる厚さまで第二の絶縁樹脂層113を形成し、半導体チップが所定の厚みになるまで第二の絶縁樹脂層と半導体チップとを研削し、その上に第一の絶縁層114を形成し、電極104を露出させる開口部を絶縁樹脂層に形成し、導電性の材料で配線117と端子121を形成し、半導体ウエハを所定の厚さに研削した後、素子領域の境界線に沿って個片化する。【選択図】図8