CIRCUIT DEVICE HAVING THREE-DIMENSIONAL WIRING, METHOD FOR FORMING THREE-DIMENSIONAL WIRING, AND A COMPOSITION FOR METAL FILM FORMATION FOR THREE-DIMENSIONAL WIRING
PROBLEM TO BE SOLVED: To provide a circuit device having three-dimensional wiring with good conductivity, which makes possible to readily manufacture the three-dimensional wiring with a relatively high productivity at a relatively low manufacturing cost.SOLUTION: A silicon through wiring board 1 hav...
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| creator | KOBAYASHI ATSUSHI OKITA KENZO ARITOME ISAO MATSUMOTO TAICHI SHIMODA SUGIO WATABE KAZUTO |
| description | PROBLEM TO BE SOLVED: To provide a circuit device having three-dimensional wiring with good conductivity, which makes possible to readily manufacture the three-dimensional wiring with a relatively high productivity at a relatively low manufacturing cost.SOLUTION: A silicon through wiring board 1 having three-dimensional wiring arranged so that an upper wiring 12a and a lower wiring 13a are electrically connected to each other by a contact plug 14a is manufactured. The contact plug CP includes a bottom part seed layer BS, a main seed layer MS, and a plug main body PB. The bottom part seed layer BS is formed by a conductor layer formed by vapor deposition. The main seed layer MS is formed by heating a coating film of a composition for metal film formation which includes at least one of a salt of a metal selected from Group X and Group XI of the periodic table and particles thereof.SELECTED DRAWING: Figure 1
【課題】導電性が良好な３次元配線を有し、当該３次元配線を比較的高い生産性の下に、かつ比較的低い製造コストの下に製造することが容易な３次元配線を有する回路装置を提供する。【解決手段】上側配線１２ａと下側配線１３ａとがコンタクトプラグ１４ａによって互いに電気的に接続されている３次元配線を有するシリコン貫通配線基板１を作製するにあたって、コンタクトプラグＣＰを底部シード層ＢＳと主シード層ＭＳとプラグ本体ＰＢとで構成すると共に、底部シード層ＢＳは気相蒸着法によって形成された導電体の層で形成し、主シード層ＭＳは、周期表の第１０族および第１１族から選ばれる金属の塩および粒子の少なくとも一方を含有する金属膜形成用組成物の塗膜を加熱することで形成する。【選択図】図１ |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2016048779A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2016048779A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2016048779A3</originalsourceid><addsrcrecordid>eNrjZFji7BnkHOoZouDiGubp7Krg4Rjm6eeuEOIR5Oqq6-Lp6-oX7Onv5-ijEO4ZBJTQUfB1DfHwd1Fw8w8CYV_8ih39XBQcFZz9fQP8gz1DgHJgfUAjgGrcPH18wUY4wiVwGcTDwJqWmFOcyguluRmU3FxDnD10Uwvy41OLCxKTU_NSS-K9AowMDM0MTCzMzS0djYlSBAAKXkaB</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CIRCUIT DEVICE HAVING THREE-DIMENSIONAL WIRING, METHOD FOR FORMING THREE-DIMENSIONAL WIRING, AND A COMPOSITION FOR METAL FILM FORMATION FOR THREE-DIMENSIONAL WIRING</title><source>esp@cenet</source><creator>KOBAYASHI ATSUSHI ; OKITA KENZO ; ARITOME ISAO ; MATSUMOTO TAICHI ; SHIMODA SUGIO ; WATABE KAZUTO</creator><creatorcontrib>KOBAYASHI ATSUSHI ; OKITA KENZO ; ARITOME ISAO ; MATSUMOTO TAICHI ; SHIMODA SUGIO ; WATABE KAZUTO</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a circuit device having three-dimensional wiring with good conductivity, which makes possible to readily manufacture the three-dimensional wiring with a relatively high productivity at a relatively low manufacturing cost.SOLUTION: A silicon through wiring board 1 having three-dimensional wiring arranged so that an upper wiring 12a and a lower wiring 13a are electrically connected to each other by a contact plug 14a is manufactured. The contact plug CP includes a bottom part seed layer BS, a main seed layer MS, and a plug main body PB. The bottom part seed layer BS is formed by a conductor layer formed by vapor deposition. The main seed layer MS is formed by heating a coating film of a composition for metal film formation which includes at least one of a salt of a metal selected from Group X and Group XI of the periodic table and particles thereof.SELECTED DRAWING: Figure 1
【課題】導電性が良好な３次元配線を有し、当該３次元配線を比較的高い生産性の下に、かつ比較的低い製造コストの下に製造することが容易な３次元配線を有する回路装置を提供する。【解決手段】上側配線１２ａと下側配線１３ａとがコンタクトプラグ１４ａによって互いに電気的に接続されている３次元配線を有するシリコン貫通配線基板１を作製するにあたって、コンタクトプラグＣＰを底部シード層ＢＳと主シード層ＭＳとプラグ本体ＰＢとで構成すると共に、底部シード層ＢＳは気相蒸着法によって形成された導電体の層で形成し、主シード層ＭＳは、周期表の第１０族および第１１族から選ばれる金属の塩および粒子の少なくとも一方を含有する金属膜形成用組成物の塗膜を加熱することで形成する。【選択図】図１</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; CABLES ; CONDUCTORS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INSULATORS ; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES ; SEMICONDUCTOR DEVICES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160407&DB=EPODOC&CC=JP&NR=2016048779A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160407&DB=EPODOC&CC=JP&NR=2016048779A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KOBAYASHI ATSUSHI</creatorcontrib><creatorcontrib>OKITA KENZO</creatorcontrib><creatorcontrib>ARITOME ISAO</creatorcontrib><creatorcontrib>MATSUMOTO TAICHI</creatorcontrib><creatorcontrib>SHIMODA SUGIO</creatorcontrib><creatorcontrib>WATABE KAZUTO</creatorcontrib><title>CIRCUIT DEVICE HAVING THREE-DIMENSIONAL WIRING, METHOD FOR FORMING THREE-DIMENSIONAL WIRING, AND A COMPOSITION FOR METAL FILM FORMATION FOR THREE-DIMENSIONAL WIRING</title><description>PROBLEM TO BE SOLVED: To provide a circuit device having three-dimensional wiring with good conductivity, which makes possible to readily manufacture the three-dimensional wiring with a relatively high productivity at a relatively low manufacturing cost.SOLUTION: A silicon through wiring board 1 having three-dimensional wiring arranged so that an upper wiring 12a and a lower wiring 13a are electrically connected to each other by a contact plug 14a is manufactured. The contact plug CP includes a bottom part seed layer BS, a main seed layer MS, and a plug main body PB. The bottom part seed layer BS is formed by a conductor layer formed by vapor deposition. The main seed layer MS is formed by heating a coating film of a composition for metal film formation which includes at least one of a salt of a metal selected from Group X and Group XI of the periodic table and particles thereof.SELECTED DRAWING: Figure 1
【課題】導電性が良好な３次元配線を有し、当該３次元配線を比較的高い生産性の下に、かつ比較的低い製造コストの下に製造することが容易な３次元配線を有する回路装置を提供する。【解決手段】上側配線１２ａと下側配線１３ａとがコンタクトプラグ１４ａによって互いに電気的に接続されている３次元配線を有するシリコン貫通配線基板１を作製するにあたって、コンタクトプラグＣＰを底部シード層ＢＳと主シード層ＭＳとプラグ本体ＰＢとで構成すると共に、底部シード層ＢＳは気相蒸着法によって形成された導電体の層で形成し、主シード層ＭＳは、周期表の第１０族および第１１族から選ばれる金属の塩および粒子の少なくとも一方を含有する金属膜形成用組成物の塗膜を加熱することで形成する。【選択図】図１</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CABLES</subject><subject>CONDUCTORS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INSULATORS</subject><subject>SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFji7BnkHOoZouDiGubp7Krg4Rjm6eeuEOIR5Oqq6-Lp6-oX7Onv5-ijEO4ZBJTQUfB1DfHwd1Fw8w8CYV_8ih39XBQcFZz9fQP8gz1DgHJgfUAjgGrcPH18wUY4wiVwGcTDwJqWmFOcyguluRmU3FxDnD10Uwvy41OLCxKTU_NSS-K9AowMDM0MTCzMzS0djYlSBAAKXkaB</recordid><startdate>20160407</startdate><enddate>20160407</enddate><creator>KOBAYASHI ATSUSHI</creator><creator>OKITA KENZO</creator><creator>ARITOME ISAO</creator><creator>MATSUMOTO TAICHI</creator><creator>SHIMODA SUGIO</creator><creator>WATABE KAZUTO</creator><scope>EVB</scope></search><sort><creationdate>20160407</creationdate><title>CIRCUIT DEVICE HAVING THREE-DIMENSIONAL WIRING, METHOD FOR FORMING THREE-DIMENSIONAL WIRING, AND A COMPOSITION FOR METAL FILM FORMATION FOR THREE-DIMENSIONAL WIRING</title><author>KOBAYASHI ATSUSHI ; OKITA KENZO ; ARITOME ISAO ; MATSUMOTO TAICHI ; SHIMODA SUGIO ; WATABE KAZUTO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2016048779A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2016</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CABLES</topic><topic>CONDUCTORS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INSULATORS</topic><topic>SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KOBAYASHI ATSUSHI</creatorcontrib><creatorcontrib>OKITA KENZO</creatorcontrib><creatorcontrib>ARITOME ISAO</creatorcontrib><creatorcontrib>MATSUMOTO TAICHI</creatorcontrib><creatorcontrib>SHIMODA SUGIO</creatorcontrib><creatorcontrib>WATABE KAZUTO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KOBAYASHI ATSUSHI</au><au>OKITA KENZO</au><au>ARITOME ISAO</au><au>MATSUMOTO TAICHI</au><au>SHIMODA SUGIO</au><au>WATABE KAZUTO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CIRCUIT DEVICE HAVING THREE-DIMENSIONAL WIRING, METHOD FOR FORMING THREE-DIMENSIONAL WIRING, AND A COMPOSITION FOR METAL FILM FORMATION FOR THREE-DIMENSIONAL WIRING</title><date>2016-04-07</date><risdate>2016</risdate><abstract>PROBLEM TO BE SOLVED: To provide a circuit device having three-dimensional wiring with good conductivity, which makes possible to readily manufacture the three-dimensional wiring with a relatively high productivity at a relatively low manufacturing cost.SOLUTION: A silicon through wiring board 1 having three-dimensional wiring arranged so that an upper wiring 12a and a lower wiring 13a are electrically connected to each other by a contact plug 14a is manufactured. The contact plug CP includes a bottom part seed layer BS, a main seed layer MS, and a plug main body PB. The bottom part seed layer BS is formed by a conductor layer formed by vapor deposition. The main seed layer MS is formed by heating a coating film of a composition for metal film formation which includes at least one of a salt of a metal selected from Group X and Group XI of the periodic table and particles thereof.SELECTED DRAWING: Figure 1
【課題】導電性が良好な３次元配線を有し、当該３次元配線を比較的高い生産性の下に、かつ比較的低い製造コストの下に製造することが容易な３次元配線を有する回路装置を提供する。【解決手段】上側配線１２ａと下側配線１３ａとがコンタクトプラグ１４ａによって互いに電気的に接続されている３次元配線を有するシリコン貫通配線基板１を作製するにあたって、コンタクトプラグＣＰを底部シード層ＢＳと主シード層ＭＳとプラグ本体ＰＢとで構成すると共に、底部シード層ＢＳは気相蒸着法によって形成された導電体の層で形成し、主シード層ＭＳは、周期表の第１０族および第１１族から選ばれる金属の塩および粒子の少なくとも一方を含有する金属膜形成用組成物の塗膜を加熱することで形成する。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CABLES CONDUCTORS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INSULATORS SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES SEMICONDUCTOR DEVICES |
| title | CIRCUIT DEVICE HAVING THREE-DIMENSIONAL WIRING, METHOD FOR FORMING THREE-DIMENSIONAL WIRING, AND A COMPOSITION FOR METAL FILM FORMATION FOR THREE-DIMENSIONAL WIRING |
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