SEMICONDUCTOR PACKAGE
PROBLEM TO BE SOLVED: To provide a lamination type semiconductor package which reduces heat transmitted from a lower chip to an upper chip.SOLUTION: A lamination type semiconductor package according to an embodiment includes: a first semiconductor package including a first circuit board and a first...
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| creator | TAMAGAWA MICHIAKI WATANABE SHINJI KUMAGAI KINICHI MIYAKOSHI TAKESHI MATSUBARA HIROAKI SAKUMOTO SHOTARO NAKAMURA TAKU DEMACHI HIROSHI HOSOYAMADA SUMIKAZU NAKAMURA SHINGO CHIKAI TOMOYA IWASAKI TOSHIHIRO ISHIDO KIMINORI HONDA HIROKAZU |
| description | PROBLEM TO BE SOLVED: To provide a lamination type semiconductor package which reduces heat transmitted from a lower chip to an upper chip.SOLUTION: A lamination type semiconductor package according to an embodiment includes: a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package laminated on the first semiconductor package; and a heat conduction material disposed on the first semiconductor element and the first circuit board located around the first semiconductor element.SELECTED DRAWING: Figure 1
【課題】積層型半導体パッケージにおいて、下側のチップから上側のチップへの伝熱を軽減する半導体パッケージを提供することを目的とする。【解決手段】本発明の一実施形態に係る積層型半導体パッケージは、第１の回路基板と第１の回路基板に実装された第１の半導体素子を含む第１の半導体パッケージと、第２の回路基板と第２の回路基板に実装された第２の半導体素子を含み第１の半導体パッケージに積層された第２の半導体パッケージと、第１の半導体素子上及び第１の半導体素子の周辺の第１の回路基板上に配置される熱伝導材料と、を有する。【選択図】図１ |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2016025294A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2016025294A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2016025294A3</originalsourceid><addsrcrecordid>eNrjZBANdvX1dPb3cwl1DvEPUghwdPZ2dHflYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBoZmBkamRpYmjsZEKQIA2LIfWQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR PACKAGE</title><source>esp@cenet</source><creator>TAMAGAWA MICHIAKI ; WATANABE SHINJI ; KUMAGAI KINICHI ; MIYAKOSHI TAKESHI ; MATSUBARA HIROAKI ; SAKUMOTO SHOTARO ; NAKAMURA TAKU ; DEMACHI HIROSHI ; HOSOYAMADA SUMIKAZU ; NAKAMURA SHINGO ; CHIKAI TOMOYA ; IWASAKI TOSHIHIRO ; ISHIDO KIMINORI ; HONDA HIROKAZU</creator><creatorcontrib>TAMAGAWA MICHIAKI ; WATANABE SHINJI ; KUMAGAI KINICHI ; MIYAKOSHI TAKESHI ; MATSUBARA HIROAKI ; SAKUMOTO SHOTARO ; NAKAMURA TAKU ; DEMACHI HIROSHI ; HOSOYAMADA SUMIKAZU ; NAKAMURA SHINGO ; CHIKAI TOMOYA ; IWASAKI TOSHIHIRO ; ISHIDO KIMINORI ; HONDA HIROKAZU</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a lamination type semiconductor package which reduces heat transmitted from a lower chip to an upper chip.SOLUTION: A lamination type semiconductor package according to an embodiment includes: a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package laminated on the first semiconductor package; and a heat conduction material disposed on the first semiconductor element and the first circuit board located around the first semiconductor element.SELECTED DRAWING: Figure 1
【課題】積層型半導体パッケージにおいて、下側のチップから上側のチップへの伝熱を軽減する半導体パッケージを提供することを目的とする。【解決手段】本発明の一実施形態に係る積層型半導体パッケージは、第１の回路基板と第１の回路基板に実装された第１の半導体素子を含む第１の半導体パッケージと、第２の回路基板と第２の回路基板に実装された第２の半導体素子を含み第１の半導体パッケージに積層された第２の半導体パッケージと、第１の半導体素子上及び第１の半導体素子の周辺の第１の回路基板上に配置される熱伝導材料と、を有する。【選択図】図１</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160208&DB=EPODOC&CC=JP&NR=2016025294A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160208&DB=EPODOC&CC=JP&NR=2016025294A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TAMAGAWA MICHIAKI</creatorcontrib><creatorcontrib>WATANABE SHINJI</creatorcontrib><creatorcontrib>KUMAGAI KINICHI</creatorcontrib><creatorcontrib>MIYAKOSHI TAKESHI</creatorcontrib><creatorcontrib>MATSUBARA HIROAKI</creatorcontrib><creatorcontrib>SAKUMOTO SHOTARO</creatorcontrib><creatorcontrib>NAKAMURA TAKU</creatorcontrib><creatorcontrib>DEMACHI HIROSHI</creatorcontrib><creatorcontrib>HOSOYAMADA SUMIKAZU</creatorcontrib><creatorcontrib>NAKAMURA SHINGO</creatorcontrib><creatorcontrib>CHIKAI TOMOYA</creatorcontrib><creatorcontrib>IWASAKI TOSHIHIRO</creatorcontrib><creatorcontrib>ISHIDO KIMINORI</creatorcontrib><creatorcontrib>HONDA HIROKAZU</creatorcontrib><title>SEMICONDUCTOR PACKAGE</title><description>PROBLEM TO BE SOLVED: To provide a lamination type semiconductor package which reduces heat transmitted from a lower chip to an upper chip.SOLUTION: A lamination type semiconductor package according to an embodiment includes: a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package laminated on the first semiconductor package; and a heat conduction material disposed on the first semiconductor element and the first circuit board located around the first semiconductor element.SELECTED DRAWING: Figure 1
【課題】積層型半導体パッケージにおいて、下側のチップから上側のチップへの伝熱を軽減する半導体パッケージを提供することを目的とする。【解決手段】本発明の一実施形態に係る積層型半導体パッケージは、第１の回路基板と第１の回路基板に実装された第１の半導体素子を含む第１の半導体パッケージと、第２の回路基板と第２の回路基板に実装された第２の半導体素子を含み第１の半導体パッケージに積層された第２の半導体パッケージと、第１の半導体素子上及び第１の半導体素子の周辺の第１の回路基板上に配置される熱伝導材料と、を有する。【選択図】図１</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBANdvX1dPb3cwl1DvEPUghwdPZ2dHflYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBoZmBkamRpYmjsZEKQIA2LIfWQ</recordid><startdate>20160208</startdate><enddate>20160208</enddate><creator>TAMAGAWA MICHIAKI</creator><creator>WATANABE SHINJI</creator><creator>KUMAGAI KINICHI</creator><creator>MIYAKOSHI TAKESHI</creator><creator>MATSUBARA HIROAKI</creator><creator>SAKUMOTO SHOTARO</creator><creator>NAKAMURA TAKU</creator><creator>DEMACHI HIROSHI</creator><creator>HOSOYAMADA SUMIKAZU</creator><creator>NAKAMURA SHINGO</creator><creator>CHIKAI TOMOYA</creator><creator>IWASAKI TOSHIHIRO</creator><creator>ISHIDO KIMINORI</creator><creator>HONDA HIROKAZU</creator><scope>EVB</scope></search><sort><creationdate>20160208</creationdate><title>SEMICONDUCTOR PACKAGE</title><author>TAMAGAWA MICHIAKI ; WATANABE SHINJI ; KUMAGAI KINICHI ; MIYAKOSHI TAKESHI ; MATSUBARA HIROAKI ; SAKUMOTO SHOTARO ; NAKAMURA TAKU ; DEMACHI HIROSHI ; HOSOYAMADA SUMIKAZU ; NAKAMURA SHINGO ; CHIKAI TOMOYA ; IWASAKI TOSHIHIRO ; ISHIDO KIMINORI ; HONDA HIROKAZU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2016025294A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2016</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>TAMAGAWA MICHIAKI</creatorcontrib><creatorcontrib>WATANABE SHINJI</creatorcontrib><creatorcontrib>KUMAGAI KINICHI</creatorcontrib><creatorcontrib>MIYAKOSHI TAKESHI</creatorcontrib><creatorcontrib>MATSUBARA HIROAKI</creatorcontrib><creatorcontrib>SAKUMOTO SHOTARO</creatorcontrib><creatorcontrib>NAKAMURA TAKU</creatorcontrib><creatorcontrib>DEMACHI HIROSHI</creatorcontrib><creatorcontrib>HOSOYAMADA SUMIKAZU</creatorcontrib><creatorcontrib>NAKAMURA SHINGO</creatorcontrib><creatorcontrib>CHIKAI TOMOYA</creatorcontrib><creatorcontrib>IWASAKI TOSHIHIRO</creatorcontrib><creatorcontrib>ISHIDO KIMINORI</creatorcontrib><creatorcontrib>HONDA HIROKAZU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TAMAGAWA MICHIAKI</au><au>WATANABE SHINJI</au><au>KUMAGAI KINICHI</au><au>MIYAKOSHI TAKESHI</au><au>MATSUBARA HIROAKI</au><au>SAKUMOTO SHOTARO</au><au>NAKAMURA TAKU</au><au>DEMACHI HIROSHI</au><au>HOSOYAMADA SUMIKAZU</au><au>NAKAMURA SHINGO</au><au>CHIKAI TOMOYA</au><au>IWASAKI TOSHIHIRO</au><au>ISHIDO KIMINORI</au><au>HONDA HIROKAZU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR PACKAGE</title><date>2016-02-08</date><risdate>2016</risdate><abstract>PROBLEM TO BE SOLVED: To provide a lamination type semiconductor package which reduces heat transmitted from a lower chip to an upper chip.SOLUTION: A lamination type semiconductor package according to an embodiment includes: a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package laminated on the first semiconductor package; and a heat conduction material disposed on the first semiconductor element and the first circuit board located around the first semiconductor element.SELECTED DRAWING: Figure 1
【課題】積層型半導体パッケージにおいて、下側のチップから上側のチップへの伝熱を軽減する半導体パッケージを提供することを目的とする。【解決手段】本発明の一実施形態に係る積層型半導体パッケージは、第１の回路基板と第１の回路基板に実装された第１の半導体素子を含む第１の半導体パッケージと、第２の回路基板と第２の回路基板に実装された第２の半導体素子を含み第１の半導体パッケージに積層された第２の半導体パッケージと、第１の半導体素子上及び第１の半導体素子の周辺の第１の回路基板上に配置される熱伝導材料と、を有する。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | SEMICONDUCTOR PACKAGE |
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