DESIGN DEVICE, DESIGN METHOD, AND DESIGN PROGRAM

PROBLEM TO BE SOLVED: To efficiently implement logic synthesis and place/route by inhibiting an occurrence of wiring congestion and increase in a layout area.SOLUTION: The design device generates a logic cone 400, and calculates an area ratio of a triangle Im, with a logic cell on an m-th stage between an input stage and an output stage, and input sides FF380 at both ends of input stages connected to the input thereof defined as vertices, to a triangle On, with output sides FF300 of the output stage and logic cells at both ends of the m-th stage connected to the input thereof defined as vertices. The design device sets an input stage-side first logic cone part and an output stage-side second logic cone part from the m-th stage where the calculated area ratio turns out a prescribed ratio, to a logic synthesis unit, and implements the logic synthesis using the set logic synthesis unit. 【課題】配線混雑の発生とレイアウト面積の増大を抑えて、効率的に論理合成、配置配線を行う。【解決手段】設計装置は、ロジックコーン４００を生成し、入力段と出力段の間にあるｍ段の論理セルとその入力に繋がる入力段両端の入力側ＦＦ３８０とを頂点とする三角形Ｉｍと、出力段の出力側ＦＦ３００とその入力に繋がるｍ段両端の論理セルとを頂点とする三角形Ｏｎとの面積比を算出する。設計装置は、算出した面積比が所定比となるｍ段から入力段側の第１ロジックコーン部及び出力段側の第２ロジックコーン部を論理合成単位に設定し、設定した論理合成単位を用いて論理合成を行う。【選択図】図３０