SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce an inductance component included in internal wiring to achieve a sufficient surge voltage inhibiting effect.SOLUTION: A semiconductor device comprises: a P terminal wiring pattern 51 for a P terminal and an N terminal wiring pattern 52 for an N terminal; mounting parts P11-P13 formed on three allocation regions allocated on the P terminal wiring pattern 51 for a U-phase circuit part 5U, a V-phase circuit part 5V and a W-phase circuit part 5W allocated, respectively; and mounting parts P21-P23 formed on three allocation regions allocated on the N terminal wiring pattern 52 for the U-phase circuit part 5U, the V-phase circuit part 5V and the W-phase circuit part 5W, respectively. The mounting parts P11-P13 and P21-P23 have a snubber circuit mounting structure capable of attaching or detaching corresponding mounted terminals 81 and 82 of the snubber circuit 8. 【課題】内部配線に含まれるインダクタンス成分の低減を図り、十分なサージ電圧抑制効果を実現可能な半導体装置を得る。【解決手段】Ｐ端子用のＰ端子配線パターン５１とＮ端子用のＮ端子配線パターン５２とを形成し、装着部Ｐ１１〜Ｐ１３はＰ端子配線パターン５１上にＵ相回路部５Ｕ、Ｖ相回路部５Ｖ及びＷ相回路部５Ｗ用に割り当てられた３つの割り当て領域上に形成され、装着部Ｐ２１〜Ｐ２３は、Ｎ端子配線パターン５２上にＵ相回路部５Ｕ、Ｖ相回路部５Ｖ及びＷ相回路部５Ｗ用に割り当てられた３つの割り当て領域上に形成される。これら装着部Ｐ１１〜Ｐ１３及びＰ２１〜Ｐ２３は、対応するスナバ回路８の被装着端子８１及び８２を着脱可能なスナバ回路装着構造を有している。【選択図】図２