SEMICONDUCTOR PACKAGE

PROBLEM TO BE SOLVED: To provide a lamination type semiconductor package which reduces heat transferred from a lower chip to an upper chip.SOLUTION: A lamination type semiconductor package according to one embodiment of the invention includes: a first circuit board; a first semiconductor package whe...

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Bibliographische Detailangaben
Hauptverfasser: HOSOYAMADA SUMIKAZU, NAKAMURA SHINGO, CHIKAI TOMOYA, KUMAGAI KINICHI, MIYAKOSHI TAKESHI, MATSUBARA HIROAKI, SAKUMOTO SHOTARO
Format: Patent
Sprache:eng ; jpn
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide a lamination type semiconductor package which reduces heat transferred from a lower chip to an upper chip.SOLUTION: A lamination type semiconductor package according to one embodiment of the invention includes: a first circuit board; a first semiconductor package where a first semiconductor element is mounted on the first circuit board; a second circuit board; a second semiconductor package where a second semiconductor element is mounted on the second circuit board, the second semiconductor package laminated on the first semiconductor package; a sealing resin which seals the first semiconductor element; a conductor layer which is disposed contacting with the sealing resin; and a thermal via which is connected with the conductive layer and disposed on the first circuit board. 【課題】積層型半導体パッケージにおいて、下側のチップから上側のチップへの伝熱を軽減する半導体パッケージを提供することを目的とする。【解決手段】本発明の一実施形態に係る積層型半導体パッケージは、第1の回路基板と、第1の回路基板に第1の半導体素子が実装された第1の半導体パッケージと、第2の回路基板と、第2の回路基板に第2の半導体素子が実装され、第1の半導体パッケージに積層された第2の半導体パッケージと、第1の半導体を封止する封止樹脂と、封止樹脂に接して配置される導電層と、導電層と接続し第1の回路基板上に配置されるサーマルビアと、を有する。【選択図】図1