VOLTAGE FOLLOWER CIRCUIT
PROBLEM TO BE SOLVED: To provide a voltage follower circuit capable of increasing current driving capability while suppressing increases in power consumption of an OP amplifier and a chip area.SOLUTION: A voltage follower circuit (100 to 104) comprises: an OP amplifier (10) in which one terminal of...
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Format: | Patent |
Sprache: | eng ; jpn |
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Zusammenfassung: | PROBLEM TO BE SOLVED: To provide a voltage follower circuit capable of increasing current driving capability while suppressing increases in power consumption of an OP amplifier and a chip area.SOLUTION: A voltage follower circuit (100 to 104) comprises: an OP amplifier (10) in which one terminal of a pair of differential input terminals is connected to an input terminal and the other terminal is connected to an output terminal; a circuit (J1 or R1) which forms a current path between a second power supply terminal (VSS) supplied with a second DC voltage (VSS) lower than a first DC voltage (VDD2) and an output terminal (POUT); and output transistors (MN1, MP1, NPN1, and PNP1). A first main electrode of the output transistor is connected to a first power terminal (P2) supplied with the first DC voltage. A second main electrode of the output transistor is connected to the output terminal. A control electrode of the output transistor is supplied with an output signal of the OP amplifier.
【課題】OPアンプの消費電流とチップ面積の増大を抑えつつ、電流駆動能力を増大させることができるボルテージフォロア回路を提供する。【解決手段】本発明に係るボルテージフォロア回路(100〜104)は、差動入力端子の一方が前記入力端子に接続され、他方が前記出力端子に接続されるOPアンプ(10)と、第1直流電圧(VDD2)よりも低い第2直流電圧(VSS)が供給される第2電源端子(VSS)と出力端子(POUT)との間に電流経路を形成する回路(J1、R1)と、出力トランジスタ(MN1、MP1、NPN1、PNP1)とを有し、前記出力トランジスタの第1主電極が前記第1直流電圧が供給される第1電源端子(P2)に接続され、前記出力トランジスタの第2主電極が前記出力端子に接続され、前記出力トランジスタの制御電極に前記OPアンプの出力信号が供給されることを特徴とする。【選択図】図1 |
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