SIGNAL PROCESSING CIRCUIT
PROBLEM TO BE SOLVED: To provide a signal processing circuit capable of avoiding oscillation in a case where a positive feedback path, from an output terminal to a positive input terminal of an operational amplifier in an integrating circuit, exists.SOLUTION: Since a switch SW2 is turned off in an i...
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| creator | SHINOI KIYOSHI |
| description | PROBLEM TO BE SOLVED: To provide a signal processing circuit capable of avoiding oscillation in a case where a positive feedback path, from an output terminal to a positive input terminal of an operational amplifier in an integrating circuit, exists.SOLUTION: Since a switch SW2 is turned off in an integration mode, a positive feedback path from an output terminal to a positive input terminal (+) of an operational amplifier 16 is interrupted. Consequently, oscillation can be avoided even if the voltage of a signal line, connected with a reference voltage supply point 53, varies due to the fact that the impedance at the reference voltage supply point 53 is not 0. In the integration mode, a resistor 40 and a capacitor C2 function as a noise filter. In a reset mode, the switch SW2 is turned on, and charges are accumulated in the capacitor C2 depending on a reference voltage VREF2 at the reference voltage supply point 53.
【課題】、積分回路のオペアンプの出力端子から正入力端子への正帰還経路が存在する場合において、発振を回避することができる信号処理回路を提供する。【解決手段】 積分モードにおいて、スイッチＳＷ２がオフになるため、オペアンプ１６の出力端子から正入力端子（＋）への正帰還経路が遮断される。そのため、参照電圧供給点５３のインピーダンスが０ではないことに起因して参照電圧供給点５３に接続される信号線の電圧が変動しても、発振することを回避できる。積分モードにおいて、抵抗４０とキャパシタＣ２がノイズフィルタとして機能する。また、リセットモードにおいて、スイッチＳＷ２がオンになり、参照電圧供給点５３の参照電圧ＶＲＥＦ２に応じてキャパシタＣ２に電荷が蓄積される。【選択図】図１ |
| format | Patent |
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【課題】、積分回路のオペアンプの出力端子から正入力端子への正帰還経路が存在する場合において、発振を回避することができる信号処理回路を提供する。【解決手段】 積分モードにおいて、スイッチＳＷ２がオフになるため、オペアンプ１６の出力端子から正入力端子（＋）への正帰還経路が遮断される。そのため、参照電圧供給点５３のインピーダンスが０ではないことに起因して参照電圧供給点５３に接続される信号線の電圧が変動しても、発振することを回避できる。積分モードにおいて、抵抗４０とキャパシタＣ２がノイズフィルタとして機能する。また、リセットモードにおいて、スイッチＳＷ２がオンになり、参照電圧供給点５３の参照電圧ＶＲＥＦ２に応じてキャパシタＣ２に電荷が蓄積される。【選択図】図１</description><language>eng ; jpn</language><subject>AMPLIFIERS ; ANALOGUE COMPUTERS ; BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRICITY ; IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; PULSE TECHNIQUE ; RESONATORS ; TESTING</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150813&DB=EPODOC&CC=JP&NR=2015146496A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150813&DB=EPODOC&CC=JP&NR=2015146496A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHINOI KIYOSHI</creatorcontrib><title>SIGNAL PROCESSING CIRCUIT</title><description>PROBLEM TO BE SOLVED: To provide a signal processing circuit capable of avoiding oscillation in a case where a positive feedback path, from an output terminal to a positive input terminal of an operational amplifier in an integrating circuit, exists.SOLUTION: Since a switch SW2 is turned off in an integration mode, a positive feedback path from an output terminal to a positive input terminal (+) of an operational amplifier 16 is interrupted. Consequently, oscillation can be avoided even if the voltage of a signal line, connected with a reference voltage supply point 53, varies due to the fact that the impedance at the reference voltage supply point 53 is not 0. In the integration mode, a resistor 40 and a capacitor C2 function as a noise filter. In a reset mode, the switch SW2 is turned on, and charges are accumulated in the capacitor C2 depending on a reference voltage VREF2 at the reference voltage supply point 53.
【課題】、積分回路のオペアンプの出力端子から正入力端子への正帰還経路が存在する場合において、発振を回避することができる信号処理回路を提供する。【解決手段】 積分モードにおいて、スイッチＳＷ２がオフになるため、オペアンプ１６の出力端子から正入力端子（＋）への正帰還経路が遮断される。そのため、参照電圧供給点５３のインピーダンスが０ではないことに起因して参照電圧供給点５３に接続される信号線の電圧が変動しても、発振することを回避できる。積分モードにおいて、抵抗４０とキャパシタＣ２がノイズフィルタとして機能する。また、リセットモードにおいて、スイッチＳＷ２がオンになり、参照電圧供給点５３の参照電圧ＶＲＥＦ２に応じてキャパシタＣ２に電荷が蓄積される。【選択図】図１</description><subject>AMPLIFIERS</subject><subject>ANALOGUE COMPUTERS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRICITY</subject><subject>IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>RESONATORS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAM9nT3c_RRCAjyd3YNDvb0c1dw9gxyDvUM4WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgaGpoYmZiaWZo7GRCkCAFtcII4</recordid><startdate>20150813</startdate><enddate>20150813</enddate><creator>SHINOI KIYOSHI</creator><scope>EVB</scope></search><sort><creationdate>20150813</creationdate><title>SIGNAL PROCESSING CIRCUIT</title><author>SHINOI KIYOSHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2015146496A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2015</creationdate><topic>AMPLIFIERS</topic><topic>ANALOGUE COMPUTERS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRICITY</topic><topic>IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>RESONATORS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>SHINOI KIYOSHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHINOI KIYOSHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SIGNAL PROCESSING CIRCUIT</title><date>2015-08-13</date><risdate>2015</risdate><abstract>PROBLEM TO BE SOLVED: To provide a signal processing circuit capable of avoiding oscillation in a case where a positive feedback path, from an output terminal to a positive input terminal of an operational amplifier in an integrating circuit, exists.SOLUTION: Since a switch SW2 is turned off in an integration mode, a positive feedback path from an output terminal to a positive input terminal (+) of an operational amplifier 16 is interrupted. Consequently, oscillation can be avoided even if the voltage of a signal line, connected with a reference voltage supply point 53, varies due to the fact that the impedance at the reference voltage supply point 53 is not 0. In the integration mode, a resistor 40 and a capacitor C2 function as a noise filter. In a reset mode, the switch SW2 is turned on, and charges are accumulated in the capacitor C2 depending on a reference voltage VREF2 at the reference voltage supply point 53.
【課題】、積分回路のオペアンプの出力端子から正入力端子への正帰還経路が存在する場合において、発振を回避することができる信号処理回路を提供する。【解決手段】 積分モードにおいて、スイッチＳＷ２がオフになるため、オペアンプ１６の出力端子から正入力端子（＋）への正帰還経路が遮断される。そのため、参照電圧供給点５３のインピーダンスが０ではないことに起因して参照電圧供給点５３に接続される信号線の電圧が変動しても、発振することを回避できる。積分モードにおいて、抵抗４０とキャパシタＣ２がノイズフィルタとして機能する。また、リセットモードにおいて、スイッチＳＷ２がオンになり、参照電圧供給点５３の参照電圧ＶＲＥＦ２に応じてキャパシタＣ２に電荷が蓄積される。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | AMPLIFIERS ANALOGUE COMPUTERS BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRICITY IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS PULSE TECHNIQUE RESONATORS TESTING |
| title | SIGNAL PROCESSING CIRCUIT |
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