EPITAXIAL WAFER FOR HETEROJUNCTION BIPOLAR TRANSISTORS, AND HETEROJUNCTION BIPOLAR TRANSISTOR ELEMENT
PROBLEM TO BE SOLVED: To provide an epitaxial wafer for heterojunction bipolar transistors and a heterojunction bipolar transistor element which enable the increase in current gain while minimizing a turn-on voltage.SOLUTION: An epitaxial wafer 100 for heterojunction bipolar transistors comprises: a...
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| creator | FUJIO SHINJIRO |
| description | PROBLEM TO BE SOLVED: To provide an epitaxial wafer for heterojunction bipolar transistors and a heterojunction bipolar transistor element which enable the increase in current gain while minimizing a turn-on voltage.SOLUTION: An epitaxial wafer 100 for heterojunction bipolar transistors comprises: a base layer 105 made of InGaAs(0 |
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【課題】ターンオン電圧を最大限に低下させると共に電流利得を向上させることが可能なヘテロ接合バイポーラトランジスタ用エピタキシャルウェハ及びヘテロ接合バイポーラトランジスタ素子を提供する。【解決手段】エネルギ障壁低減層１０４は、Ｉｎ組成がベース層１０５側からコレクタ層１０３側にかけて低下するＩｎx→0Ｇａ1-x→1Ａｓ（０＜ｘ ０．１０）からなると共に層厚が３０ｎｍ未満であり、ベース層１０５は、ＩｎyＧａ1-yＡｓ（０＜ｙ ０．１０）からなり、エミッタ層１０６は、ＩｎzＧａ1-zＰ（０．４８ ｚ ０．５８）からなり、エネルギ障壁低減層１０４とベース層１０５とエミッタ層１０６の合計層厚が１００ｎｍ以下であるヘテロ接合バイポーラトランジスタ用エピタキシャルウェハ１００である。【選択図】図１</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150518&DB=EPODOC&CC=JP&NR=2015095552A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150518&DB=EPODOC&CC=JP&NR=2015095552A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FUJIO SHINJIRO</creatorcontrib><title>EPITAXIAL WAFER FOR HETEROJUNCTION BIPOLAR TRANSISTORS, AND HETEROJUNCTION BIPOLAR TRANSISTOR ELEMENT</title><description>PROBLEM TO BE SOLVED: To provide an epitaxial wafer for heterojunction bipolar transistors and a heterojunction bipolar transistor element which enable the increase in current gain while minimizing a turn-on voltage.SOLUTION: An epitaxial wafer 100 for heterojunction bipolar transistors comprises: a base layer 105 made of InGaAs(0<y≤0.10); a collector layer 103; an energy barrier-reduction layer 104 made of InGaAs(0<x≤0.10), where the composition of In decreases from the base layer 105 toward the collector layer 103, of which the thickness is less than 30 nm; and an emitter layer 106 made of InGaP(0.48≤z≤0.58). The total layer thickness of the energy barrier-reduction layer 104, the base layer 105, and the emitter layer 106 is 100 nm or less.
【課題】ターンオン電圧を最大限に低下させると共に電流利得を向上させることが可能なヘテロ接合バイポーラトランジスタ用エピタキシャルウェハ及びヘテロ接合バイポーラトランジスタ素子を提供する。【解決手段】エネルギ障壁低減層１０４は、Ｉｎ組成がベース層１０５側からコレクタ層１０３側にかけて低下するＩｎx→0Ｇａ1-x→1Ａｓ（０＜ｘ ０．１０）からなると共に層厚が３０ｎｍ未満であり、ベース層１０５は、ＩｎyＧａ1-yＡｓ（０＜ｙ ０．１０）からなり、エミッタ層１０６は、ＩｎzＧａ1-zＰ（０．４８ ｚ ０．５８）からなり、エネルギ障壁低減層１０４とベース層１０５とエミッタ層１０６の合計層厚が１００ｎｍ以下であるヘテロ接合バイポーラトランジスタ用エピタキシャルウェハ１００である。【選択図】図１</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZEh1DfAMcYzwdPRRCHd0cw1ScPMPUvBwDXEN8vcK9XMO8fT3U3DyDPD3cQxSCAly9Av2DA7xDwrWUXD0cyGsTsHVx9XX1S-Eh4E1LTGnOJUXSnMzKLm5hjh76KYW5MenFhckJqfmpZbEewUYGRiaGliampoaORoTpQgAT7s2Aw</recordid><startdate>20150518</startdate><enddate>20150518</enddate><creator>FUJIO SHINJIRO</creator><scope>EVB</scope></search><sort><creationdate>20150518</creationdate><title>EPITAXIAL WAFER FOR HETEROJUNCTION BIPOLAR TRANSISTORS, AND HETEROJUNCTION BIPOLAR TRANSISTOR ELEMENT</title><author>FUJIO SHINJIRO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2015095552A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2015</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>FUJIO SHINJIRO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FUJIO SHINJIRO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>EPITAXIAL WAFER FOR HETEROJUNCTION BIPOLAR TRANSISTORS, AND HETEROJUNCTION BIPOLAR TRANSISTOR ELEMENT</title><date>2015-05-18</date><risdate>2015</risdate><abstract>PROBLEM TO BE SOLVED: To provide an epitaxial wafer for heterojunction bipolar transistors and a heterojunction bipolar transistor element which enable the increase in current gain while minimizing a turn-on voltage.SOLUTION: An epitaxial wafer 100 for heterojunction bipolar transistors comprises: a base layer 105 made of InGaAs(0<y≤0.10); a collector layer 103; an energy barrier-reduction layer 104 made of InGaAs(0<x≤0.10), where the composition of In decreases from the base layer 105 toward the collector layer 103, of which the thickness is less than 30 nm; and an emitter layer 106 made of InGaP(0.48≤z≤0.58). The total layer thickness of the energy barrier-reduction layer 104, the base layer 105, and the emitter layer 106 is 100 nm or less.
【課題】ターンオン電圧を最大限に低下させると共に電流利得を向上させることが可能なヘテロ接合バイポーラトランジスタ用エピタキシャルウェハ及びヘテロ接合バイポーラトランジスタ素子を提供する。【解決手段】エネルギ障壁低減層１０４は、Ｉｎ組成がベース層１０５側からコレクタ層１０３側にかけて低下するＩｎx→0Ｇａ1-x→1Ａｓ（０＜ｘ ０．１０）からなると共に層厚が３０ｎｍ未満であり、ベース層１０５は、ＩｎyＧａ1-yＡｓ（０＜ｙ ０．１０）からなり、エミッタ層１０６は、ＩｎzＧａ1-zＰ（０．４８ ｚ ０．５８）からなり、エネルギ障壁低減層１０４とベース層１０５とエミッタ層１０６の合計層厚が１００ｎｍ以下であるヘテロ接合バイポーラトランジスタ用エピタキシャルウェハ１００である。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | EPITAXIAL WAFER FOR HETEROJUNCTION BIPOLAR TRANSISTORS, AND HETEROJUNCTION BIPOLAR TRANSISTOR ELEMENT |
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