SEMICONDUCTOR DEVICE AND WRITING METHOD THEREOF

PROBLEM TO BE SOLVED: To store information with a wider reading margin by using as a storage element a resistance change type element for which forming is not performed, thereby improving the reliability of information storage.SOLUTION: A semiconductor device includes a memory cell array having a pl...

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Hauptverfasser: TSUKADA SHUICHI, KINO YUSUKE, MAEDA AKIKO
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:PROBLEM TO BE SOLVED: To store information with a wider reading margin by using as a storage element a resistance change type element for which forming is not performed, thereby improving the reliability of information storage.SOLUTION: A semiconductor device includes a memory cell array having a plurality of memory cells. Each of the memory cells includes a resistance change type element including a first electrode and second electrode sandwiching a variable resistor, in which after a forming voltage is applied between the first electrode and second electrode, an electric resistance of the variable resistor reversibly changes according to the application of a write voltage between the first electrode and second electrode. The memory cell array includes: first memory cells that are memory cells to which the forming voltage is applied; and second memory cells to which the forming voltage is not applied. The second memory cells are constituted so as to store one of a mutually different first logical value and second logical value constituting first information, for example, control information. 【課題】フォーミングしない抵抗変化型素子を記憶素子として利用し、より広い読み出しマージンで情報を記憶させ、情報記憶信頼性を向上させる。【解決手段】該半導体装置は、それぞれが、可変抵抗体を挟む第1電極及び第2電極を備え、第1電極と第2電極との間にフォーミング電圧を印加した後、第1電極と第2電極との間の書込電圧の印加に応じて可変抵抗体の電気抵抗が可逆的に変化する抵抗変化型素子を備える複数のメモリセルを有するメモリセルアレイを備える。該メモリセルアレイは、フォーミング電圧を印加するメモリセルである第1メモリセルと、フォーミング電圧を印加しないメモリセルである第2メモリセルと、を含み、第2メモリセルは、第1情報、例えば制御情報、を構成する互いに異なる第1論理値及び第2論理値のうちの一方を記憶するように構成される。【選択図】図1