ELECTRONIC DEVICE

PROBLEM TO BE SOLVED: To alleviate the influence of undesired signal reflection on branch wiring lines even if a branch path branched off from a main wiring line by fly-by topology is long.SOLUTION: On a mounting substrate on which a plurality of first semiconductor components operating synchronousl...

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Bibliographische Detailangaben
Hauptverfasser: HAYASHI TORU, SUWA MOTOHIRO
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:PROBLEM TO BE SOLVED: To alleviate the influence of undesired signal reflection on branch wiring lines even if a branch path branched off from a main wiring line by fly-by topology is long.SOLUTION: On a mounting substrate on which a plurality of first semiconductor components operating synchronously with a clock signal and a second semiconductor component controlling those first semiconductor components are mounted, a plurality of main wiring lines and branch wiring lines branched off at a plurality of branch points from the respective main wiring lines are provided as signal paths electrically connecting the second semiconductor component to the first semiconductor components, a chip resistor being connected in series halfway along the branch wiring line from the branch point that does not overlap the first semiconductor component and located at a distant position to the corresponding first semiconductor component. 【課題】フライバイトポロジによる主配線から分岐した分岐経路が長くても分岐配線上での不所望な信号反射による影響を緩和する。【解決手段】クロック信号に同期動作する複数の第1半導体部品とそれらを制御する第2半導体部品とが実装される実装基板に、前記第2半導体部品と複数個の前記第1半導体部品とを電気的に接続する信号経路として、複数個の主配線と、夫々の主配線における複数の分岐点で夫々分岐した分岐配線とを設け、第1半導体部品とは重ならずに離間した位置にある前記分岐点に関しては、そこから対応する第1半導体部品に至る分岐配線の途中にチップ抵抗を直列に接続する。【選択図】図1