MULTILAYER SUBSTRATE AND MANUFACTURING METHOD THEREFOR

PROBLEM TO BE SOLVED: To suppress short circuit between interconnections due to voids generated between inner layer interconnections, in a multilayer board produced by laminating a build-up layer, consisting of a prepreg, on the outer surface of a core layer as an insulation layer, and then sealing...

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Bibliographische Detailangaben
Hauptverfasser: KISHIMOTO KEIJI, YABUTA EIJI
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:PROBLEM TO BE SOLVED: To suppress short circuit between interconnections due to voids generated between inner layer interconnections, in a multilayer board produced by laminating a build-up layer, consisting of a prepreg, on the outer surface of a core layer as an insulation layer, and then sealing a plurality of inner layer interconnections provided on the outer surface with resin of the build-up layer.SOLUTION: The part positioned between a plurality of inner layer interconnections 51, 52, out of the front and back surfaces 20a, 20b of a core layer 20, are uneven surfaces 21a, 21b having a surface roughness larger than that of a part where the plurality of inner layer interconnections 51, 52 are positioned. 【課題】絶縁層としてのコア層の外面にプリプレグよりなるビルドアップ層を積層し、当該外面に設けられた複数の内層配線をビルドアップ層の樹脂で封止してなる多層基板において、内層配線間に発生するボイドによる当該配線間の短絡を抑制する。【解決手段】コア層20の表裏面20a、20bのうち複数の内層配線51、52間に位置する部位は、複数の内層配線51、52が位置する部位よりも表面粗さが大きい凹凸面21a、21bとされている。【選択図】図2