PROGRAM ANALYSIS APPARATUS, AND PROGRAM ANALYSIS METHOD

PROBLEM TO BE SOLVED: To perform efficient decompile.SOLUTION: An input/output analysis part 121 analyzes an input instruction and stores information concerned with the input instruction in an instruction information table 35, and after ending the analysis of the input instruction, an arithmetic ins...

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Hauptverfasser: TERAE NAO, YUMITATSU MASAHIRO, SHIMIZU KATSUTO, NAKAMIGAWA TETSUAKI, MASUKO NAOYA
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:PROBLEM TO BE SOLVED: To perform efficient decompile.SOLUTION: An input/output analysis part 121 analyzes an input instruction and stores information concerned with the input instruction in an instruction information table 35, and after ending the analysis of the input instruction, an arithmetic instruction analysis part 122 performs arithmetic instruction analysis for storing information concerned with an arithmetic instruction in the instruction information table 35. After end of the arithmetic instruction analysis, the input/output analysis part 121 performs output instruction analysis for storing information concerned with an output instruction in the instruction information table 35, and after end of the output instruction analysis, a conversion part 123 generates device elements in a ladder diagram on the basis of the instruction information table 35. 【課題】効率的な逆コンパイルを行うことを課題とする。【解決手段】入出力解析部121が入力命令を解析し、入力命令に関する情報を命令情報テーブル35に格納し、入力命令の解析終了後、演算命令解析部122が、演算命令に関する情報を命令情報テーブル35に格納する演算命令解析を行い、演算命令解析終了後、入出力解析部121が出力命令に関する情報を命令情報テーブル35に格納する出力命令解析を行い、出力命令解析終了後、変換部123が命令情報テーブル35を基に、ラダー図におけるデバイス素子を生成することを特徴とする。【選択図】図1