SEMICONDUCTOR INTEGRATED CIRCUIT AND PATTERN LAYOUT METHOD THEREOF
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of forming a TEG (a Test Elementary Group) pattern by preventing that monitoring result has an error without reducing monitored items and without making width of a scribing region larger by using a dummy pattern.SOLUTION: A...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of forming a TEG (a Test Elementary Group) pattern by preventing that monitoring result has an error without reducing monitored items and without making width of a scribing region larger by using a dummy pattern.SOLUTION: A semiconductor integrated circuit comprises: a plurality of function modules formed in a chip; and a functional dummy pattern 5 formed in a peripheral vacant region 3 of a predetermined function module 2 in the chip and having an aberration monitoring function. The functional dummy pattern 5 is formed so that a band-shaped metal portion B and a band-shaped insulating film portion L are periodically repeated respectively in a plan view. |
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