SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To enable efficient trimming of circuits without causing increase in chip area even when including a plurality of circuits which require trimming.SOLUTION: A semiconductor integrated circuit comprises: a clock generation circuit 2 which includes a frequency adjustment transisto...

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1. Verfasser: OKAMI TAKESHI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To enable efficient trimming of circuits without causing increase in chip area even when including a plurality of circuits which require trimming.SOLUTION: A semiconductor integrated circuit comprises: a clock generation circuit 2 which includes a frequency adjustment transistor and generates a clock at a frequency dependent on an upper limit current value of the frequency adjustment transistor; an A/D conversion circuit 3 and another circuit 4 which are clock synchronization circuits that operate in synchronous with a clock, and which include a gain adjustment transistor and have an operable maximum clock frequency dependent on an upper limit current value of the gain adjustment transistor; and a constant current control circuit 1 which has reference current source having a variable current value and controls each upper limit current value of the frequency adjustment transistor and the gain adjustment transistor to be a current value proportional to a reference current value flowing through the reference current source.