SEMICONDUCTOR DEVICE
PROBLEM TO BE SOLVED: To provide a MOS transistor structure taking advantage of a fin structure to make it suitable for high integration and low voltage operation and a memory cell making the most of the MOS transistor.SOLUTION: In a semiconductor memory device, a memory cell is connected to the int...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | TSUCHIYA RYUTA ITO KIYOO |
description | PROBLEM TO BE SOLVED: To provide a MOS transistor structure taking advantage of a fin structure to make it suitable for high integration and low voltage operation and a memory cell making the most of the MOS transistor.SOLUTION: In a semiconductor memory device, a memory cell is connected to the intersection of a row line WL and a column line YSconstituting a memory cell array, the memory cell consisting of two MOS transistors Mand Mand one capacitor Cwhich stores information electric charge. One side of the two transistors is controlled by the row line WL and the other side is controlled by the column line YS, so that when a pulse voltage is applied to each of the row line WL and the column line YS, the memory cell is selected, delivering and receiving a signal to and from a data line DL. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2013229611A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2013229611A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2013229611A3</originalsourceid><addsrcrecordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhsZGRpZmhoaOxkQpAgC8kR8U</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>TSUCHIYA RYUTA ; ITO KIYOO</creator><creatorcontrib>TSUCHIYA RYUTA ; ITO KIYOO</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a MOS transistor structure taking advantage of a fin structure to make it suitable for high integration and low voltage operation and a memory cell making the most of the MOS transistor.SOLUTION: In a semiconductor memory device, a memory cell is connected to the intersection of a row line WL and a column line YSconstituting a memory cell array, the memory cell consisting of two MOS transistors Mand Mand one capacitor Cwhich stores information electric charge. One side of the two transistors is controlled by the row line WL and the other side is controlled by the column line YS, so that when a pulse voltage is applied to each of the row line WL and the column line YS, the memory cell is selected, delivering and receiving a signal to and from a data line DL.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20131107&DB=EPODOC&CC=JP&NR=2013229611A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20131107&DB=EPODOC&CC=JP&NR=2013229611A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TSUCHIYA RYUTA</creatorcontrib><creatorcontrib>ITO KIYOO</creatorcontrib><title>SEMICONDUCTOR DEVICE</title><description>PROBLEM TO BE SOLVED: To provide a MOS transistor structure taking advantage of a fin structure to make it suitable for high integration and low voltage operation and a memory cell making the most of the MOS transistor.SOLUTION: In a semiconductor memory device, a memory cell is connected to the intersection of a row line WL and a column line YSconstituting a memory cell array, the memory cell consisting of two MOS transistors Mand Mand one capacitor Cwhich stores information electric charge. One side of the two transistors is controlled by the row line WL and the other side is controlled by the column line YS, so that when a pulse voltage is applied to each of the row line WL and the column line YS, the memory cell is selected, delivering and receiving a signal to and from a data line DL.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhsZGRpZmhoaOxkQpAgC8kR8U</recordid><startdate>20131107</startdate><enddate>20131107</enddate><creator>TSUCHIYA RYUTA</creator><creator>ITO KIYOO</creator><scope>EVB</scope></search><sort><creationdate>20131107</creationdate><title>SEMICONDUCTOR DEVICE</title><author>TSUCHIYA RYUTA ; ITO KIYOO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2013229611A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>TSUCHIYA RYUTA</creatorcontrib><creatorcontrib>ITO KIYOO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TSUCHIYA RYUTA</au><au>ITO KIYOO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE</title><date>2013-11-07</date><risdate>2013</risdate><abstract>PROBLEM TO BE SOLVED: To provide a MOS transistor structure taking advantage of a fin structure to make it suitable for high integration and low voltage operation and a memory cell making the most of the MOS transistor.SOLUTION: In a semiconductor memory device, a memory cell is connected to the intersection of a row line WL and a column line YSconstituting a memory cell array, the memory cell consisting of two MOS transistors Mand Mand one capacitor Cwhich stores information electric charge. One side of the two transistors is controlled by the row line WL and the other side is controlled by the column line YS, so that when a pulse voltage is applied to each of the row line WL and the column line YS, the memory cell is selected, delivering and receiving a signal to and from a data line DL.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_JP2013229611A |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
title | SEMICONDUCTOR DEVICE |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T09%3A20%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=TSUCHIYA%20RYUTA&rft.date=2013-11-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2013229611A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |