SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a MOS transistor structure taking advantage of a fin structure to make it suitable for high integration and low voltage operation and a memory cell making the most of the MOS transistor.SOLUTION: In a semiconductor memory device, a memory cell is connected to the int...

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Bibliographische Detailangaben
Hauptverfasser: TSUCHIYA RYUTA, ITO KIYOO
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a MOS transistor structure taking advantage of a fin structure to make it suitable for high integration and low voltage operation and a memory cell making the most of the MOS transistor.SOLUTION: In a semiconductor memory device, a memory cell is connected to the intersection of a row line WL and a column line YSconstituting a memory cell array, the memory cell consisting of two MOS transistors Mand Mand one capacitor Cwhich stores information electric charge. One side of the two transistors is controlled by the row line WL and the other side is controlled by the column line YS, so that when a pulse voltage is applied to each of the row line WL and the column line YS, the memory cell is selected, delivering and receiving a signal to and from a data line DL.