MEMORY WITH WORD LEVEL POWER GATING

PROBLEM TO BE SOLVED: To provide a memory array that facilitates memory power gating.SOLUTION: According to at least one embodiment, memory power gating at word level is provided. According to at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each sub-array (e.g., each word, each row, each word line, each bit line, each portion of an array, etc.) of a memory array (11), provides fine-grained power reduction for the memory array (11). According to at least one embodiment, a gating transistor (104, 108, 112) is provided for each sub-array (e.g., each word, each row, each word line, each bit line, each portion of an array, etc.).