DELAY CIRCUIT

PROBLEM TO BE SOLVED: To provide a delay circuit that can suppress an increase in circuit scale.SOLUTION: According to one embodiment, a delay circuit 1 comprises: a transistor Tr11 that causes a gate leakage current to flow to a gate when an external input signal IN is supplied to at least any one...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: KOSUGE YOSHIHIRO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide a delay circuit that can suppress an increase in circuit scale.SOLUTION: According to one embodiment, a delay circuit 1 comprises: a transistor Tr11 that causes a gate leakage current to flow to a gate when an external input signal IN is supplied to at least any one of a source, a drain and a back gate; a transistor Tr12 for removing an AC component of the external input signal IN propagating to the gate of the transistor Tr11 via a coupling capacitance formed by the transistor Tr11; and inverters 12, 13 for detecting a voltage value based on the gate leakage current and outputting a detection result of a logic value depending on the voltage value as an external output signal OUT.