SEMICONDUCTOR TESTING APPARATUS AND SEMICONDUCTOR TEST METHOD

PROBLEM TO BE SOLVED: To provide a semiconductor testing apparatus capable of testing hysteresis characteristics while suppressing an increase in measuring times.SOLUTION: The semiconductor testing apparatus comprises: a test control circuit; a counter control circuit; and a test signal generating circuit. The counter control circuit performs count operation in accordance with an operation clock. The test signal generating circuit transmits, to a device to be tested, a test signal generated on the basis of a value obtained by adding a count signal received from the counter control circuit and a control signal received from the test control circuit. The counter control circuit feeds back an output signal of the device to be tested, and when the output signal transitions from Low to High, stops the count operation and continues to transmit the count signal of a held value. The control signal has a constant value until the N-th measurement, is a signal for causing the potential of the test signal to be a minimum hysteresis voltage at the N+1-th measurement, and is a signal for causing the potential of the test signal to be a maximum hysteresis voltage at the N+2-th measurement.