SEMICONDUCTOR MEMORY TEST METHOD AND SEMICONDUCTOR MEMORY

PROBLEM TO BE SOLVED: To prevent a verification criteria in erase test from relaxing due to influence of a memory cell which is slow in erasing, and to prevent reliability of a semiconductor memory from degrading.SOLUTION: In a semiconductor memory test method, a first erase test is performed by app...

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Bibliographische Detailangaben
Hauptverfasser: MORI IKU, YAGISHITA YOSHIMASA, AOKI HAJIME
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To prevent a verification criteria in erase test from relaxing due to influence of a memory cell which is slow in erasing, and to prevent reliability of a semiconductor memory from degrading.SOLUTION: In a semiconductor memory test method, a first erase test is performed by applying erase pulses to a memory cell group which is included in a memory cell array and divided into a plurality of groups A, B, until a group which is determined that erase is completed is detected (Step S1). A second erase test is performed on other memory cell groups including the memory cell group on the basis of the number of erase pulses when detecting a group which is determined that erase is completed first (Step S2).