CLOCK GENERATION CIRCUIT FOR LOOP ROUTE PROTECTION RELAY SYSTEM

PROBLEM TO BE SOLVED: To make it possible to reduce: the scale of reception clock circuit and transmission clock circuit of a DPLL circuit for generating a clock for each HDLC line demultiplexed; and the number of clock terminals.SOLUTION: Time-division multiplexed information transmitted/received between a central communication device and a plurality of terminal devices is transmitted through a multi-channel HDLC line. A reception circuit in the central communication device or each terminal device obtains separated data DATA(SOUT) by: first performing serial/parallel (S/P) conversion on time-division multiplexed reception data; and performing parallel/serial (P/S) conversion on the reception data by using a DPLL reception clock generated in timing of the S/P conversion. A clock generation circuit (control + DPLL) for generating the DPLL reception clock generates a common DPLL reception clock RX_DCLK by which the parallel/serial (P/S) conversion can be performed at the same timing among a plurality of channels, by controlling S/P conversion timing in performing the serial/parallel (S/P) conversion.