ROW CONVERSION CIRCUIT AND ROW CONVERSION METHOD
PROBLEM TO BE SOLVED: To provide a row conversion circuit capable of expanding a row conversion mode while suppressing the increase of a logic circuit.SOLUTION: A row conversion circuit includes: a row conversion mode setting portion 11 for setting a number N of rows after conversion; M pieces of me...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | TSUCHIDA YASUSHI YAMAGUCHI TOMIICHI ABE YASUYUKI |
description | PROBLEM TO BE SOLVED: To provide a row conversion circuit capable of expanding a row conversion mode while suppressing the increase of a logic circuit.SOLUTION: A row conversion circuit includes: a row conversion mode setting portion 11 for setting a number N of rows after conversion; M pieces of memories 12; a write address producing portion 13 for producing write address in each memory 12, and updating the write address so as to indicate a writing position of the next M-row input data; a write data control portion 14 for writing each bit of the M-row input data at a position of the write address of each memory 12; a selection signal producing portion 15 for producing a selection signal indicating N pieces of the M pieces of the memories 12, and updating the selection signal so as to indicate the next another N pieces; a read address producing portion 16 for producing a read address in each of the N pieces of memories 12 indicated by the selection signal; a read address updating control portion 17 for controlling the read address producing portion 16; and a data selection output portion 18 for reading out N-row data from the M pieces of the memories 12 according to the selection signal and the read address. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2013066083A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2013066083A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2013066083A3</originalsourceid><addsrcrecordid>eNrjZDAI8g9XcPb3C3MNCvb091Nw9gxyDvUMUXD0c1FAk_J1DfHwd-FhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhsYGZmYGFsaOxkQpAgCQ5ybo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ROW CONVERSION CIRCUIT AND ROW CONVERSION METHOD</title><source>esp@cenet</source><creator>TSUCHIDA YASUSHI ; YAMAGUCHI TOMIICHI ; ABE YASUYUKI</creator><creatorcontrib>TSUCHIDA YASUSHI ; YAMAGUCHI TOMIICHI ; ABE YASUYUKI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a row conversion circuit capable of expanding a row conversion mode while suppressing the increase of a logic circuit.SOLUTION: A row conversion circuit includes: a row conversion mode setting portion 11 for setting a number N of rows after conversion; M pieces of memories 12; a write address producing portion 13 for producing write address in each memory 12, and updating the write address so as to indicate a writing position of the next M-row input data; a write data control portion 14 for writing each bit of the M-row input data at a position of the write address of each memory 12; a selection signal producing portion 15 for producing a selection signal indicating N pieces of the M pieces of the memories 12, and updating the selection signal so as to indicate the next another N pieces; a read address producing portion 16 for producing a read address in each of the N pieces of memories 12 indicated by the selection signal; a read address updating control portion 17 for controlling the read address producing portion 16; and a data selection output portion 18 for reading out N-row data from the M pieces of the memories 12 according to the selection signal and the read address.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130411&DB=EPODOC&CC=JP&NR=2013066083A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130411&DB=EPODOC&CC=JP&NR=2013066083A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TSUCHIDA YASUSHI</creatorcontrib><creatorcontrib>YAMAGUCHI TOMIICHI</creatorcontrib><creatorcontrib>ABE YASUYUKI</creatorcontrib><title>ROW CONVERSION CIRCUIT AND ROW CONVERSION METHOD</title><description>PROBLEM TO BE SOLVED: To provide a row conversion circuit capable of expanding a row conversion mode while suppressing the increase of a logic circuit.SOLUTION: A row conversion circuit includes: a row conversion mode setting portion 11 for setting a number N of rows after conversion; M pieces of memories 12; a write address producing portion 13 for producing write address in each memory 12, and updating the write address so as to indicate a writing position of the next M-row input data; a write data control portion 14 for writing each bit of the M-row input data at a position of the write address of each memory 12; a selection signal producing portion 15 for producing a selection signal indicating N pieces of the M pieces of the memories 12, and updating the selection signal so as to indicate the next another N pieces; a read address producing portion 16 for producing a read address in each of the N pieces of memories 12 indicated by the selection signal; a read address updating control portion 17 for controlling the read address producing portion 16; and a data selection output portion 18 for reading out N-row data from the M pieces of the memories 12 according to the selection signal and the read address.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAI8g9XcPb3C3MNCvb091Nw9gxyDvUMUXD0c1FAk_J1DfHwd-FhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhsYGZmYGFsaOxkQpAgCQ5ybo</recordid><startdate>20130411</startdate><enddate>20130411</enddate><creator>TSUCHIDA YASUSHI</creator><creator>YAMAGUCHI TOMIICHI</creator><creator>ABE YASUYUKI</creator><scope>EVB</scope></search><sort><creationdate>20130411</creationdate><title>ROW CONVERSION CIRCUIT AND ROW CONVERSION METHOD</title><author>TSUCHIDA YASUSHI ; YAMAGUCHI TOMIICHI ; ABE YASUYUKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2013066083A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>TSUCHIDA YASUSHI</creatorcontrib><creatorcontrib>YAMAGUCHI TOMIICHI</creatorcontrib><creatorcontrib>ABE YASUYUKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TSUCHIDA YASUSHI</au><au>YAMAGUCHI TOMIICHI</au><au>ABE YASUYUKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ROW CONVERSION CIRCUIT AND ROW CONVERSION METHOD</title><date>2013-04-11</date><risdate>2013</risdate><abstract>PROBLEM TO BE SOLVED: To provide a row conversion circuit capable of expanding a row conversion mode while suppressing the increase of a logic circuit.SOLUTION: A row conversion circuit includes: a row conversion mode setting portion 11 for setting a number N of rows after conversion; M pieces of memories 12; a write address producing portion 13 for producing write address in each memory 12, and updating the write address so as to indicate a writing position of the next M-row input data; a write data control portion 14 for writing each bit of the M-row input data at a position of the write address of each memory 12; a selection signal producing portion 15 for producing a selection signal indicating N pieces of the M pieces of the memories 12, and updating the selection signal so as to indicate the next another N pieces; a read address producing portion 16 for producing a read address in each of the N pieces of memories 12 indicated by the selection signal; a read address updating control portion 17 for controlling the read address producing portion 16; and a data selection output portion 18 for reading out N-row data from the M pieces of the memories 12 according to the selection signal and the read address.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_JP2013066083A |
source | esp@cenet |
subjects | CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
title | ROW CONVERSION CIRCUIT AND ROW CONVERSION METHOD |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T19%3A27%3A08IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=TSUCHIDA%20YASUSHI&rft.date=2013-04-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2013066083A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |