GATE TIMING CONTROL CIRCUIT

PROBLEM TO BE SOLVED: To equalize the voltage sharing of each semiconductor switch without adjusting the operation timing thereof according to the waveform of a surge voltage caused by the semiconductor switch, load current, temperature, main circuitry, or the like.SOLUTION: In the gate timing contr...

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Bibliographische Detailangaben
Hauptverfasser: OGURA KAZUYA, URUSHIBATA SHOTA
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To equalize the voltage sharing of each semiconductor switch without adjusting the operation timing thereof according to the waveform of a surge voltage caused by the semiconductor switch, load current, temperature, main circuitry, or the like.SOLUTION: In the gate timing control circuit 3 which adjusts the timing of a gate signal being output to a plurality of semiconductor switches A and B connected in series, comparators 4 and 4 compare the pieces of Vce detection (A) and (B) of respective semiconductor switches A and B with a preset threshold to output Vce signals (A) and (B)indicating the timing of rising in the Vce detection. A time difference control unit 8 outputs gate outputs (A) and (B), generated so as to match the timing of change of the Vce signals (A) and (B), to a gate driver 2.