CMOS LOGICAL IC PACKAGE AND AN INSPECTION METHOD THEREOF
PROBLEM TO BE SOLVED: To provide a CMOS logical IC package having an electrode for inspection and an inspection method thereof.SOLUTION: There is provided a CMOS logical IC package including the electrode for inspection provided to a position adjacent to each connection electrode pad in the package...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PROBLEM TO BE SOLVED: To provide a CMOS logical IC package having an electrode for inspection and an inspection method thereof.SOLUTION: There is provided a CMOS logical IC package including the electrode for inspection provided to a position adjacent to each connection electrode pad in the package and a buffer gate. In the CMOS logical IC package inspection method, an opened failure (including disconnection failure and partial disconnection) between the connection electrode pad in the package and an electrode land of the printed wiring board is inspected by measuring a power current produced when an inspection signal of low voltage is applied to the electrode for inspection of the CMOS logical IC package mounted on a printed wiring board. |
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