DEFECT INSPECTION METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To make an inspection of presence/absence of a defect in an imprint pattern efficient.SOLUTION: A conductive layer 2 is formed on an under layer 1. An imprint pattern 4 is formed on the conductive layer 2. An electrolytic solution 6 is brought into contact with the imprint patt...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
1. Verfasser:	MATSUOKA YASUO
Format:	Patent
Sprache:	eng
Schlagworte:	AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PERFORMING OPERATIONS PHYSICS PRINTED CIRCUITS SEMICONDUCTOR DEVICES SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDEDFOR SHAPING OR JOINING OF PLASTICS TESTING TRANSPORTING WORKING OF PLASTICS WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	MATSUOKA YASUO
description	PROBLEM TO BE SOLVED: To make an inspection of presence/absence of a defect in an imprint pattern efficient.SOLUTION: A conductive layer 2 is formed on an under layer 1. An imprint pattern 4 is formed on the conductive layer 2. An electrolytic solution 6 is brought into contact with the imprint pattern 4, and an electrode 7 is brought into contact with the electrolytic solution 6. A voltage is applied between the conductive layer 2 and an electrode 6, and a current flowing between the conductive layer 2 and the electrode 7 is measured. The presence/absence of the defect of the imprint pattern 4 is determined based on the result of the measurement of the current.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2012159448A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2012159448A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2012159448A3</originalsourceid><addsrcrecordid>eNrjZPB0cXVzdQ5R8PQLDgDSnv5-Cr6uIR7-LgqOfi4Kvo5-oW6OziGhQZ5-7jAJfzeFYFdfT2d_P5dQ5xD_IAUX1zBPZ1ceBta0xJziVF4ozc2g5OYa4uyhm1qQH59aXJCYnJqXWhLvFWBkYGhkaGppYmLhaEyUIgCOGC2g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>DEFECT INSPECTION METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>MATSUOKA YASUO</creator><creatorcontrib>MATSUOKA YASUO</creatorcontrib><description>PROBLEM TO BE SOLVED: To make an inspection of presence/absence of a defect in an imprint pattern efficient.SOLUTION: A conductive layer 2 is formed on an under layer 1. An imprint pattern 4 is formed on the conductive layer 2. An electrolytic solution 6 is brought into contact with the imprint pattern 4, and an electrode 7 is brought into contact with the electrolytic solution 6. A voltage is applied between the conductive layer 2 and an electrode 6, and a current flowing between the conductive layer 2 and the electrode 7 is measured. The presence/absence of the defect of the imprint pattern 4 is determined based on the result of the measurement of the current.</description><language>eng</language><subject>AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING ; BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PERFORMING OPERATIONS ; PHYSICS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES ; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDEDFOR ; SHAPING OR JOINING OF PLASTICS ; TESTING ; TRANSPORTING ; WORKING OF PLASTICS ; WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20120823&DB=EPODOC&CC=JP&NR=2012159448A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25566,76549</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20120823&DB=EPODOC&CC=JP&NR=2012159448A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MATSUOKA YASUO</creatorcontrib><title>DEFECT INSPECTION METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE</title><description>PROBLEM TO BE SOLVED: To make an inspection of presence/absence of a defect in an imprint pattern efficient.SOLUTION: A conductive layer 2 is formed on an under layer 1. An imprint pattern 4 is formed on the conductive layer 2. An electrolytic solution 6 is brought into contact with the imprint pattern 4, and an electrode 7 is brought into contact with the electrolytic solution 6. A voltage is applied between the conductive layer 2 and an electrode 6, and a current flowing between the conductive layer 2 and the electrode 7 is measured. The presence/absence of the defect of the imprint pattern 4 is determined based on the result of the measurement of the current.</description><subject>AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PERFORMING OPERATIONS</subject><subject>PHYSICS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDEDFOR</subject><subject>SHAPING OR JOINING OF PLASTICS</subject><subject>TESTING</subject><subject>TRANSPORTING</subject><subject>WORKING OF PLASTICS</subject><subject>WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPB0cXVzdQ5R8PQLDgDSnv5-Cr6uIR7-LgqOfi4Kvo5-oW6OziGhQZ5-7jAJfzeFYFdfT2d_P5dQ5xD_IAUX1zBPZ1ceBta0xJziVF4ozc2g5OYa4uyhm1qQH59aXJCYnJqXWhLvFWBkYGhkaGppYmLhaEyUIgCOGC2g</recordid><startdate>20120823</startdate><enddate>20120823</enddate><creator>MATSUOKA YASUO</creator><scope>EVB</scope></search><sort><creationdate>20120823</creationdate><title>DEFECT INSPECTION METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE</title><author>MATSUOKA YASUO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2012159448A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><topic>AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PERFORMING OPERATIONS</topic><topic>PHYSICS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDEDFOR</topic><topic>SHAPING OR JOINING OF PLASTICS</topic><topic>TESTING</topic><topic>TRANSPORTING</topic><topic>WORKING OF PLASTICS</topic><topic>WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL</topic><toplevel>online_resources</toplevel><creatorcontrib>MATSUOKA YASUO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MATSUOKA YASUO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DEFECT INSPECTION METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE</title><date>2012-08-23</date><risdate>2012</risdate><abstract>PROBLEM TO BE SOLVED: To make an inspection of presence/absence of a defect in an imprint pattern efficient.SOLUTION: A conductive layer 2 is formed on an under layer 1. An imprint pattern 4 is formed on the conductive layer 2. An electrolytic solution 6 is brought into contact with the imprint pattern 4, and an electrode 7 is brought into contact with the electrolytic solution 6. A voltage is applied between the conductive layer 2 and an electrode 6, and a current flowing between the conductive layer 2 and the electrode 7 is measured. The presence/absence of the defect of the imprint pattern 4 is determined based on the result of the measurement of the current.</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_JP2012159448A
source	esp@cenet
subjects	AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PERFORMING OPERATIONS PHYSICS PRINTED CIRCUITS SEMICONDUCTOR DEVICES SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDEDFOR SHAPING OR JOINING OF PLASTICS TESTING TRANSPORTING WORKING OF PLASTICS WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL
title	DEFECT INSPECTION METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-17T23%3A20%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MATSUOKA%20YASUO&rft.date=2012-08-23&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2012159448A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true