INTEGRATED-CIRCUIT LAYOUT DESIGN METHOD, LAYOUT DESIGN DEVICE AND DESIGN PROGRAM

PROBLEM TO BE SOLVED: To prevent a new setup time violation from occurring when correcting a hold time violation by inserting a delay element into a logical element path including a high drive element.SOLUTION: A layout design method includes: a step for applying arrangement and wiring to an integra...

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Bibliographische Detailangaben

1. Verfasser:	HAYASHIDA HIROMI
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES
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