INTEGRATED-CIRCUIT LAYOUT DESIGN METHOD, LAYOUT DESIGN DEVICE AND DESIGN PROGRAM

PROBLEM TO BE SOLVED: To prevent a new setup time violation from occurring when correcting a hold time violation by inserting a delay element into a logical element path including a high drive element.SOLUTION: A layout design method includes: a step for applying arrangement and wiring to an integrated circuit that includes a first flip-flop 101, a second flip-flop 102 and a logical circuit between output of the first flip-flop 101 and input of the second flip-flop 102; a step for detecting a hold time violation; and a step for inserting a delay element 302 in order to correct the hold time violation. In the step for inserting the delay element 302, it is confirmed whether or not a high drive element 105 is arranged in a logical element path between the first flip-flop 101 and the second flip-flop 102, and when it is confirmed that the high drive element 105 is arranged, the delay element 302 is arranged so as not to be connected directly to output of the high drive element 105.