PROCESSOR AND VECTOR LOAD INSTRUCTION EXECUTION METHOD

PROBLEM TO BE SOLVED: To execute a vector load instruction in a speculative manner and conceal memory access latency.SOLUTION: A processor of the present invention includes: an instruction issuance unit for issuing a vector load instruction read out from a main storage on the basis of branch prediction about a branch destination of an branch instruction; a data acquisition unit for starting issuing plural acquisition requests for acquiring plural pieces of vector data on the basis of the issued vector load instruction from the main storage; a determination unit for, after the branch destination of the branch instruction is determined, determining whether or not the branch prediction is fulfilled; and a vector load management unit for, when the determination unit determines that the branch prediction is fulfilled, acquiring all the vector data on the basis of the plural acquisition requests and then transferring all the vector data to a vector register, and when the determination unit determines that the branch prediction is not fulfilled, discarding the vector data acquired by the acquisition requests issued by the data acquisition unit.