LAYOUT DATA ERROR DETERMINATION METHOD, LAYOUT DATA ERROR DETERMINATION DEVICE, LAYOUT DATA CREATION DEVICE, LAYOUT DATA ERROR DETERMINATION PROGRAM

LAYOUT DATA ERROR DETERMINATION METHOD, LAYOUT DATA ERROR DETERMINATION DEVICE, LAYOUT DATA CREATION DEVICE, LAYOUT DATA ERROR DETERMINATION PROGRAM

PROBLEM TO BE SOLVED: To provide a layout data error determination method, a layout data error determination device, a layout data creation device, and a layout data error determination program capable of easily creating layout data for determination, and eliminating pseudo errors from a design rule...

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1. Verfasser: HOSHINO NAOHIKO
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator HOSHINO NAOHIKO
description PROBLEM TO BE SOLVED: To provide a layout data error determination method, a layout data error determination device, a layout data creation device, and a layout data error determination program capable of easily creating layout data for determination, and eliminating pseudo errors from a design rule check result by previously predicting portions where pseudo errors may appear in the layout data.SOLUTION: The layout data error determination method includes a layout verification step and a design rule determination step. The design rule determination step has an error identifier application step and an error confirmation step.
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The design rule determination step has an error identifier application step and an error confirmation step.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120329&amp;DB=EPODOC&amp;CC=JP&amp;NR=2012064032A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120329&amp;DB=EPODOC&amp;CC=JP&amp;NR=2012064032A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HOSHINO NAOHIKO</creatorcontrib><title>LAYOUT DATA ERROR DETERMINATION METHOD, LAYOUT DATA ERROR DETERMINATION DEVICE, LAYOUT DATA CREATION DEVICE, LAYOUT DATA ERROR DETERMINATION PROGRAM</title><description>PROBLEM TO BE SOLVED: To provide a layout data error determination method, a layout data error determination device, a layout data creation device, and a layout data error determination program capable of easily creating layout data for determination, and eliminating pseudo errors from a design rule check result by previously predicting portions where pseudo errors may appear in the layout data.SOLUTION: The layout data error determination method includes a layout verification step and a design rule determination step. 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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title LAYOUT DATA ERROR DETERMINATION METHOD, LAYOUT DATA ERROR DETERMINATION DEVICE, LAYOUT DATA CREATION DEVICE, LAYOUT DATA ERROR DETERMINATION PROGRAM
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