MULTI-CORE PROCESSOR SYSTEM AND MULTI-CORE PROCESSOR

PROBLEM TO BE SOLVED: To maintain, with software, consistency of a cache in a memory area to which only an access utilizing the cache is allowed.SOLUTION: A state manager classifies an area allocated to a corresponding multi-core processor within a first memory area into a first state in which the a...

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Bibliographische Detailangaben
Hauptverfasser:	ODAKA TAKESHI, TAKEDA AKIRA
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS PHYSICS TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE
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Beschreibung
Zusammenfassung:	PROBLEM TO BE SOLVED: To maintain, with software, consistency of a cache in a memory area to which only an access utilizing the cache is allowed.SOLUTION: A state manager classifies an area allocated to a corresponding multi-core processor within a first memory area into a first state in which the area is not allocated to processor cores, a second state in which the area is allocated to one of the processor cores and read and write are performed, and a third state in which the area is allocated to one or more of the processor cores and read and write are prohibited, and executes a transition between the states. A cache/memory manager writes back a corresponding cache when the state manager causes a transition from the second state to the third state.