TILED PREFETCH AND CACHED DEPTH BUFFER

TILED PREFETCH AND CACHED DEPTH BUFFER

PROBLEM TO BE SOLVED: To pipeline a prefetch mechanism that provides cache of depth tile in a 3D graphic processing.SOLUTION: A prefetch mechanism can be stored in advance in cache predictively using a triangular geometric information in a previous pipeline step, thereby improving efficiency of memo...

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Bibliographische Detailangaben
Hauptverfasser: JOFFREY SIPPY, RAJAT RAJINDER KUMAR DHAWAN, MICHAEL HUGH ANDERSON, DAN MINGLUN CHUANG
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To pipeline a prefetch mechanism that provides cache of depth tile in a 3D graphic processing.SOLUTION: A prefetch mechanism can be stored in advance in cache predictively using a triangular geometric information in a previous pipeline step, thereby improving efficiency of memory bandwidth usage. A z value compression technique can be used optionally in consideration of a further reduction of electric power consumption and the memory bandwidth.