PACKET MULTIPLEXER

PROBLEM TO BE SOLVED: To provide a packet multiplexer capable of inserting an appropriate inter-packet gap between packets even if the transmission speed of a communication line is accelerated, and packets having a wider data width are multiplexed due to multiple bit expansion.SOLUTION: A first to nth buffers 1-1 to 1-n each comprises: an FIFO pre-stage processor 2; reception packet FIFOs 3-1 to 3-n; a packet arrival information generator 4; a packet length measurement section 5; a reception packet FIFO reading controller 6; a packet interval adjustment controller 7; packet interval adjusters 8-1 to 8-n; and an MUX 9 in the buffer. The packet interval adjusters 8-1 to 8-n receive packets from the reception packet FIFOs 3-1 to 3-n of each line, and adjust a location of the first bite of each of the reception packets by responding to an inter-packet gap of the packet interval information.