CACHE DEVICE AND INFORMATION PROCESSOR

PROBLEM TO BE SOLVED: To provide a software error correction method exerting a little influence on the performance of a processor performing a pipeline processing.SOLUTION: A data array 43 stores data and a parity bit, and a check bit array 46 stores a ECC bit of the data. A parity check unit 44 acquires, by a read request from a processor 1, read object data and the parity bit thereof from the data array 43 to perform the parity check of the read object data using the parity bit. When detecting data error, the parity check unit outputs a stall command signal to command a pipeline stall to the processor 1. An error correction unit 47 acquires the ECC bit of the read object data from the check bit array 46 during the pipeline stall, corrects the error of the read object data using the ECC bit and outputs the read object data after the error correction and a stall cancel signal to command the cancel of the pipeline stall to the processor 1.