OUTPUT BUFFER CIRCUIT

PROBLEM TO BE SOLVED: To provide an output buffer circuit capable of high-speed operation where an output impedance of the output buffer circuit having a pre-emphasis function is constant without depending on an adjustable amount of pre-emphasis and a number of pre-emphasis taps and operation timing, and matches with a characteristic impedance of a transmission line, and does not cause re-reflection at an output terminal of the output buffer.SOLUTION: In an output buffer circuit that includes inverter 1-3, delay circuits 1-3 that give a certain delay time and buffers 1-3, and has a function of transmitting a logic signal into a transmission channel, and generating a waveform having four or more kinds of signal voltages on the transmitting side in accordance with a signal attenuation amount of the transmission channel, the amount of pre-emphasis is made to be variable, and an on-resistance Rs of the buffer is made to be constant. The output buffer circuit includes selector circuits 1-3 in the pre-stage of the buffer, and is capable of selecting, by the selector logic, signals input into the buffer and inverts the data signal in the inverter, and adjusts the amount of pre-emphasis and the number of pre-emphasis taps by the select signal of the selector logic.