SEMICONDUCTOR INTEGRATED CIRCUIT AND PATTERN LAYOUT METHOD THEREOF

SEMICONDUCTOR INTEGRATED CIRCUIT AND PATTERN LAYOUT METHOD THEREOF

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of preventing a dummy pattern from bending and preventing a part of the dummy pattern from missing even if a mechanical stress is applied to the dummy pattern during CMP processing and the pattern layout method thereof.SOLUT...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: KAMON KAZUYA
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of preventing a dummy pattern from bending and preventing a part of the dummy pattern from missing even if a mechanical stress is applied to the dummy pattern during CMP processing and the pattern layout method thereof.SOLUTION: The semiconductor integrated circuit comprises predetermined functional regions and a dummy pattern DMP1 formed on a space area SP1. The space area SP1 is positioned between the predetermined functional regions. The dummy pattern DMP1 is formed in a frame shape and comprises: a first metal part MT1 that defines a periphery ED of the dummy pattern DMP1; a second metal part MT2 that is positioned on an internal circumferential side of the first metal part MT1 and formed to be continuous to the first metal part MT1; and a plurality of non-forming regions NT positioned in a area where the second metal part MT2 is not formed on the internal circumference side of the first metal part MT1.