CIRCUIT OPERATION VERIFICATION SYSTEM AND VERIFICATION ENVIRONMENT CONFIGURATION METHOD
PROBLEM TO BE SOLVED: To achieve high-speed operation verification of a semiconductor integrated circuit, and to secure flexibility and controllability relative to the operation verification.SOLUTION: A circuit operation verification system includes a computer, a programmable logic device constituti...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | SUWA MITSUNORI |
| description | PROBLEM TO BE SOLVED: To achieve high-speed operation verification of a semiconductor integrated circuit, and to secure flexibility and controllability relative to the operation verification.SOLUTION: A circuit operation verification system includes a computer, a programmable logic device constituting a circuit to be tested, a test bench unit for performing operation verification of the circuit to be tested. The test bench unit includes a software portion achieved by the execution of software by the computer and a hardware portion configured on the programmable logic device together with the circuit to be tested. The hardware portion has a hardware function which generates a test pattern and conducts an operation verification by inputting the test pattern to the circuit to be tested. The hardware function can be controlled by changing a control parameter. The software portion variably sets the control parameter. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2011203857A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2011203857A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2011203857A3</originalsourceid><addsrcrecordid>eNrjZAh39gxyDvUMUfAPcA1yDPH091MIcw3ydPN0hnCCI4NDXH0VHP1cUMVd_cI8g_z9fF39QhSc_f3cPN1Dodp9XUM8_F14GFjTEnOKU3mhNDeDkptriLOHbmpBfnxqcUFicmpeakm8V4CRgaGhkYGxham5ozFRigCAtDIc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CIRCUIT OPERATION VERIFICATION SYSTEM AND VERIFICATION ENVIRONMENT CONFIGURATION METHOD</title><source>esp@cenet</source><creator>SUWA MITSUNORI</creator><creatorcontrib>SUWA MITSUNORI</creatorcontrib><description>PROBLEM TO BE SOLVED: To achieve high-speed operation verification of a semiconductor integrated circuit, and to secure flexibility and controllability relative to the operation verification.SOLUTION: A circuit operation verification system includes a computer, a programmable logic device constituting a circuit to be tested, a test bench unit for performing operation verification of the circuit to be tested. The test bench unit includes a software portion achieved by the execution of software by the computer and a hardware portion configured on the programmable logic device together with the circuit to be tested. The hardware portion has a hardware function which generates a test pattern and conducts an operation verification by inputting the test pattern to the circuit to be tested. The hardware function can be controlled by changing a control parameter. The software portion variably sets the control parameter.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20111013&DB=EPODOC&CC=JP&NR=2011203857A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20111013&DB=EPODOC&CC=JP&NR=2011203857A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SUWA MITSUNORI</creatorcontrib><title>CIRCUIT OPERATION VERIFICATION SYSTEM AND VERIFICATION ENVIRONMENT CONFIGURATION METHOD</title><description>PROBLEM TO BE SOLVED: To achieve high-speed operation verification of a semiconductor integrated circuit, and to secure flexibility and controllability relative to the operation verification.SOLUTION: A circuit operation verification system includes a computer, a programmable logic device constituting a circuit to be tested, a test bench unit for performing operation verification of the circuit to be tested. The test bench unit includes a software portion achieved by the execution of software by the computer and a hardware portion configured on the programmable logic device together with the circuit to be tested. The hardware portion has a hardware function which generates a test pattern and conducts an operation verification by inputting the test pattern to the circuit to be tested. The hardware function can be controlled by changing a control parameter. The software portion variably sets the control parameter.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAh39gxyDvUMUfAPcA1yDPH091MIcw3ydPN0hnCCI4NDXH0VHP1cUMVd_cI8g_z9fF39QhSc_f3cPN1Dodp9XUM8_F14GFjTEnOKU3mhNDeDkptriLOHbmpBfnxqcUFicmpeakm8V4CRgaGhkYGxham5ozFRigCAtDIc</recordid><startdate>20111013</startdate><enddate>20111013</enddate><creator>SUWA MITSUNORI</creator><scope>EVB</scope></search><sort><creationdate>20111013</creationdate><title>CIRCUIT OPERATION VERIFICATION SYSTEM AND VERIFICATION ENVIRONMENT CONFIGURATION METHOD</title><author>SUWA MITSUNORI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2011203857A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SUWA MITSUNORI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SUWA MITSUNORI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CIRCUIT OPERATION VERIFICATION SYSTEM AND VERIFICATION ENVIRONMENT CONFIGURATION METHOD</title><date>2011-10-13</date><risdate>2011</risdate><abstract>PROBLEM TO BE SOLVED: To achieve high-speed operation verification of a semiconductor integrated circuit, and to secure flexibility and controllability relative to the operation verification.SOLUTION: A circuit operation verification system includes a computer, a programmable logic device constituting a circuit to be tested, a test bench unit for performing operation verification of the circuit to be tested. The test bench unit includes a software portion achieved by the execution of software by the computer and a hardware portion configured on the programmable logic device together with the circuit to be tested. The hardware portion has a hardware function which generates a test pattern and conducts an operation verification by inputting the test pattern to the circuit to be tested. The hardware function can be controlled by changing a control parameter. The software portion variably sets the control parameter.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_JP2011203857A |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | CIRCUIT OPERATION VERIFICATION SYSTEM AND VERIFICATION ENVIRONMENT CONFIGURATION METHOD |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T18%3A46%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SUWA%20MITSUNORI&rft.date=2011-10-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2011203857A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |