SEMICONDUCTOR MEMORY DEVICE

PROBLEM TO BE SOLVED: To provide a memory which can suppress increase of a data reading period and increase of a power consumption when the data reading operation are separately executed for one bit line and another bit line of adjacent bit lines.SOLUTION: The device includes: a memory cell array co...

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Bibliographische Detailangaben
Hauptverfasser: MAKINO HIDEKAZU, IWAI MAKOTO
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a memory which can suppress increase of a data reading period and increase of a power consumption when the data reading operation are separately executed for one bit line and another bit line of adjacent bit lines.SOLUTION: The device includes: a memory cell array consisting of memory cells which are arrayed at gate intervals of ≤30 nm; a sense amplifier for detecting data stored in the memory cells by detecting a current which flows through the bit lines into the memory cells connected to selection word lines; and a word line driver for applying a voltage to the word line when the data are written into the memory cells. The sense amplifier detects the data of respective memory cells connected to the adjacent first bit line and second bit line respectively in different periods. The word line driver maintains a potential of at least one word line in a period between the data detecting operation of the memory cell connected to the first bit line and the data detecting operation of the memory cell connected to the second bit line.