SUBSTRATE PROCESSING METHOD

SUBSTRATE PROCESSING METHOD

PROBLEM TO BE SOLVED: To provide a substrate processing method reducing variations in line widths of first and second resist patterns between substrates and in a substrate surface when forming minute resist patterns by double patterning. SOLUTION: The substrate processing method includes: first proc...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: NIWA TAKAFUMI, NAKAMURA YASUYUKI, KYODA HIDEJI
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator NIWA TAKAFUMI
NAKAMURA YASUYUKI
KYODA HIDEJI
description PROBLEM TO BE SOLVED: To provide a substrate processing method reducing variations in line widths of first and second resist patterns between substrates and in a substrate surface when forming minute resist patterns by double patterning. SOLUTION: The substrate processing method includes: first processing processes S13-S16 of exposing a substrate formed with a first resist film and forming a first resist pattern by a heating process and a development process; and second processing processes S17-S20 of forming a second resist film on the substrate formed with the first resist pattern, exposing the substrate formed with the second resist film, and forming a second resist pattern by the heating process and development process. A first processing condition of first processing processes S22-S25 is corrected based on a measurement value of the line width of the second resist pattern formed on one substrate, and a second processing condition of second processing processes S26-S29 is corrected based on a measurement value of the line width of the first resist pattern formed on one substrate. COPYRIGHT: (C)2011,JPO&INPIT
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2011166027A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2011166027A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2011166027A3</originalsourceid><addsrcrecordid>eNrjZJAODnUKDglyDHFVCAjyd3YNDvb0c1fwdQ3x8HfhYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBoaGhmZmBkbmjsZEKQIAqeghJQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SUBSTRATE PROCESSING METHOD</title><source>esp@cenet</source><creator>NIWA TAKAFUMI ; NAKAMURA YASUYUKI ; KYODA HIDEJI</creator><creatorcontrib>NIWA TAKAFUMI ; NAKAMURA YASUYUKI ; KYODA HIDEJI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a substrate processing method reducing variations in line widths of first and second resist patterns between substrates and in a substrate surface when forming minute resist patterns by double patterning. SOLUTION: The substrate processing method includes: first processing processes S13-S16 of exposing a substrate formed with a first resist film and forming a first resist pattern by a heating process and a development process; and second processing processes S17-S20 of forming a second resist film on the substrate formed with the first resist pattern, exposing the substrate formed with the second resist film, and forming a second resist pattern by the heating process and development process. A first processing condition of first processing processes S22-S25 is corrected based on a measurement value of the line width of the second resist pattern formed on one substrate, and a second processing condition of second processing processes S26-S29 is corrected based on a measurement value of the line width of the first resist pattern formed on one substrate. COPYRIGHT: (C)2011,JPO&amp;INPIT</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20110825&amp;DB=EPODOC&amp;CC=JP&amp;NR=2011166027A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20110825&amp;DB=EPODOC&amp;CC=JP&amp;NR=2011166027A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NIWA TAKAFUMI</creatorcontrib><creatorcontrib>NAKAMURA YASUYUKI</creatorcontrib><creatorcontrib>KYODA HIDEJI</creatorcontrib><title>SUBSTRATE PROCESSING METHOD</title><description>PROBLEM TO BE SOLVED: To provide a substrate processing method reducing variations in line widths of first and second resist patterns between substrates and in a substrate surface when forming minute resist patterns by double patterning. SOLUTION: The substrate processing method includes: first processing processes S13-S16 of exposing a substrate formed with a first resist film and forming a first resist pattern by a heating process and a development process; and second processing processes S17-S20 of forming a second resist film on the substrate formed with the first resist pattern, exposing the substrate formed with the second resist film, and forming a second resist pattern by the heating process and development process. A first processing condition of first processing processes S22-S25 is corrected based on a measurement value of the line width of the second resist pattern formed on one substrate, and a second processing condition of second processing processes S26-S29 is corrected based on a measurement value of the line width of the first resist pattern formed on one substrate. COPYRIGHT: (C)2011,JPO&amp;INPIT</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAODnUKDglyDHFVCAjyd3YNDvb0c1fwdQ3x8HfhYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBoaGhmZmBkbmjsZEKQIAqeghJQ</recordid><startdate>20110825</startdate><enddate>20110825</enddate><creator>NIWA TAKAFUMI</creator><creator>NAKAMURA YASUYUKI</creator><creator>KYODA HIDEJI</creator><scope>EVB</scope></search><sort><creationdate>20110825</creationdate><title>SUBSTRATE PROCESSING METHOD</title><author>NIWA TAKAFUMI ; NAKAMURA YASUYUKI ; KYODA HIDEJI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2011166027A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>NIWA TAKAFUMI</creatorcontrib><creatorcontrib>NAKAMURA YASUYUKI</creatorcontrib><creatorcontrib>KYODA HIDEJI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NIWA TAKAFUMI</au><au>NAKAMURA YASUYUKI</au><au>KYODA HIDEJI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SUBSTRATE PROCESSING METHOD</title><date>2011-08-25</date><risdate>2011</risdate><abstract>PROBLEM TO BE SOLVED: To provide a substrate processing method reducing variations in line widths of first and second resist patterns between substrates and in a substrate surface when forming minute resist patterns by double patterning. SOLUTION: The substrate processing method includes: first processing processes S13-S16 of exposing a substrate formed with a first resist film and forming a first resist pattern by a heating process and a development process; and second processing processes S17-S20 of forming a second resist film on the substrate formed with the first resist pattern, exposing the substrate formed with the second resist film, and forming a second resist pattern by the heating process and development process. A first processing condition of first processing processes S22-S25 is corrected based on a measurement value of the line width of the second resist pattern formed on one substrate, and a second processing condition of second processing processes S26-S29 is corrected based on a measurement value of the line width of the first resist pattern formed on one substrate. COPYRIGHT: (C)2011,JPO&amp;INPIT</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JP2011166027A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SUBSTRATE PROCESSING METHOD
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T19%3A37%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NIWA%20TAKAFUMI&rft.date=2011-08-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2011166027A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true