PROCESS FOR FABRICATING HETEROSTRUCTURE WITH MINIMIZED STRESS

PROCESS FOR FABRICATING HETEROSTRUCTURE WITH MINIMIZED STRESS

PROBLEM TO BE SOLVED: To provide a method of suppressing peeling at and the occurrence of a defect to an edge of a substrate during bonding of a hetero-substrate. SOLUTION: A process for fabricating a heterostructure comprises a step of bonding a first wafer 110 to a second wafer 120, the first wafe...

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Bibliographische Detailangaben
1. Verfasser: VAUFREDAZ ALEXANDRE
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a method of suppressing peeling at and the occurrence of a defect to an edge of a substrate during bonding of a hetero-substrate. SOLUTION: A process for fabricating a heterostructure comprises a step of bonding a first wafer 110 to a second wafer 120, the first wafer 110 having a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer 120, and at least one bond-strengthening annealing step. The process is particularly characterized in that it comprises, after the bonding step and before the bond-strengthening annealing step, at least one trimming step in which the first wafer 110 is at least partially trimmed. COPYRIGHT: (C)2011,JPO&INPIT