MULTILAYER WIRING BOARD, AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide a multilayer wiring board and a method of manufacturing the same such that an amount of warpage can be suppressed, and operability and a yield are satisfactory even for coreless technique employed in which wiring layers are stacked only on one side of a copper foil....

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Hauptverfasser: ISHIHARA MITSUYASU, KODAIRA MASAYUKI, NISHIDA TAKANORI, ISODA SATOSHI
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creator ISHIHARA MITSUYASU
KODAIRA MASAYUKI
NISHIDA TAKANORI
ISODA SATOSHI
description PROBLEM TO BE SOLVED: To provide a multilayer wiring board and a method of manufacturing the same such that an amount of warpage can be suppressed, and operability and a yield are satisfactory even for coreless technique employed in which wiring layers are stacked only on one side of a copper foil. SOLUTION: This invention relates to: the multilayer wiring board that includes a first layer wiring pattern formed by circuit-processing a metal foil A, and at least one high layer-side wiring layer having an insulating resin layer disposed on the first layer wiring pattern and a wiring pattern disposed on the insulating resin layer, wherein a high layer-side wiring pattern is formed on the insulating resin layer by circuit-processing the metal foil and a conductor layer formed by plating, and a highest layer-side wiring pattern is larger in thickness than the first layer wiring pattern or larger in conductor layer remaining ratio than the first layer wiring pattern, or a highest layer-side insulating resin layer is smaller in thickness than the insulating resin layer on the first layer wiring pattern; and the method of manufacturing the same. COPYRIGHT: (C)2011,JPO&INPIT
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2011129563A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2011129563A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2011129563A3</originalsourceid><addsrcrecordid>eNrjZLD1DfUJ8fRxjHQNUgj3DPL0c1dw8ncMctFRcPRzUfB1DfHwd1Hwd1PwdfQLdXN0DgkFKwnxcFUIdvR15WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgaGhoZGlqZmxo7GRCkCAGj_KgQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MULTILAYER WIRING BOARD, AND METHOD OF MANUFACTURING THE SAME</title><source>esp@cenet</source><creator>ISHIHARA MITSUYASU ; KODAIRA MASAYUKI ; NISHIDA TAKANORI ; ISODA SATOSHI</creator><creatorcontrib>ISHIHARA MITSUYASU ; KODAIRA MASAYUKI ; NISHIDA TAKANORI ; ISODA SATOSHI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a multilayer wiring board and a method of manufacturing the same such that an amount of warpage can be suppressed, and operability and a yield are satisfactory even for coreless technique employed in which wiring layers are stacked only on one side of a copper foil. SOLUTION: This invention relates to: the multilayer wiring board that includes a first layer wiring pattern formed by circuit-processing a metal foil A, and at least one high layer-side wiring layer having an insulating resin layer disposed on the first layer wiring pattern and a wiring pattern disposed on the insulating resin layer, wherein a high layer-side wiring pattern is formed on the insulating resin layer by circuit-processing the metal foil and a conductor layer formed by plating, and a highest layer-side wiring pattern is larger in thickness than the first layer wiring pattern or larger in conductor layer remaining ratio than the first layer wiring pattern, or a highest layer-side insulating resin layer is smaller in thickness than the insulating resin layer on the first layer wiring pattern; and the method of manufacturing the same. COPYRIGHT: (C)2011,JPO&amp;INPIT</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20110630&amp;DB=EPODOC&amp;CC=JP&amp;NR=2011129563A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20110630&amp;DB=EPODOC&amp;CC=JP&amp;NR=2011129563A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ISHIHARA MITSUYASU</creatorcontrib><creatorcontrib>KODAIRA MASAYUKI</creatorcontrib><creatorcontrib>NISHIDA TAKANORI</creatorcontrib><creatorcontrib>ISODA SATOSHI</creatorcontrib><title>MULTILAYER WIRING BOARD, AND METHOD OF MANUFACTURING THE SAME</title><description>PROBLEM TO BE SOLVED: To provide a multilayer wiring board and a method of manufacturing the same such that an amount of warpage can be suppressed, and operability and a yield are satisfactory even for coreless technique employed in which wiring layers are stacked only on one side of a copper foil. SOLUTION: This invention relates to: the multilayer wiring board that includes a first layer wiring pattern formed by circuit-processing a metal foil A, and at least one high layer-side wiring layer having an insulating resin layer disposed on the first layer wiring pattern and a wiring pattern disposed on the insulating resin layer, wherein a high layer-side wiring pattern is formed on the insulating resin layer by circuit-processing the metal foil and a conductor layer formed by plating, and a highest layer-side wiring pattern is larger in thickness than the first layer wiring pattern or larger in conductor layer remaining ratio than the first layer wiring pattern, or a highest layer-side insulating resin layer is smaller in thickness than the insulating resin layer on the first layer wiring pattern; and the method of manufacturing the same. COPYRIGHT: (C)2011,JPO&amp;INPIT</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD1DfUJ8fRxjHQNUgj3DPL0c1dw8ncMctFRcPRzUfB1DfHwd1Hwd1PwdfQLdXN0DgkFKwnxcFUIdvR15WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgaGhoZGlqZmxo7GRCkCAGj_KgQ</recordid><startdate>20110630</startdate><enddate>20110630</enddate><creator>ISHIHARA MITSUYASU</creator><creator>KODAIRA MASAYUKI</creator><creator>NISHIDA TAKANORI</creator><creator>ISODA SATOSHI</creator><scope>EVB</scope></search><sort><creationdate>20110630</creationdate><title>MULTILAYER WIRING BOARD, AND METHOD OF MANUFACTURING THE SAME</title><author>ISHIHARA MITSUYASU ; KODAIRA MASAYUKI ; NISHIDA TAKANORI ; ISODA SATOSHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2011129563A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>ISHIHARA MITSUYASU</creatorcontrib><creatorcontrib>KODAIRA MASAYUKI</creatorcontrib><creatorcontrib>NISHIDA TAKANORI</creatorcontrib><creatorcontrib>ISODA SATOSHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ISHIHARA MITSUYASU</au><au>KODAIRA MASAYUKI</au><au>NISHIDA TAKANORI</au><au>ISODA SATOSHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MULTILAYER WIRING BOARD, AND METHOD OF MANUFACTURING THE SAME</title><date>2011-06-30</date><risdate>2011</risdate><abstract>PROBLEM TO BE SOLVED: To provide a multilayer wiring board and a method of manufacturing the same such that an amount of warpage can be suppressed, and operability and a yield are satisfactory even for coreless technique employed in which wiring layers are stacked only on one side of a copper foil. SOLUTION: This invention relates to: the multilayer wiring board that includes a first layer wiring pattern formed by circuit-processing a metal foil A, and at least one high layer-side wiring layer having an insulating resin layer disposed on the first layer wiring pattern and a wiring pattern disposed on the insulating resin layer, wherein a high layer-side wiring pattern is formed on the insulating resin layer by circuit-processing the metal foil and a conductor layer formed by plating, and a highest layer-side wiring pattern is larger in thickness than the first layer wiring pattern or larger in conductor layer remaining ratio than the first layer wiring pattern, or a highest layer-side insulating resin layer is smaller in thickness than the insulating resin layer on the first layer wiring pattern; and the method of manufacturing the same. COPYRIGHT: (C)2011,JPO&amp;INPIT</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
SEMICONDUCTOR DEVICES
title MULTILAYER WIRING BOARD, AND METHOD OF MANUFACTURING THE SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-16T00%3A06%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=ISHIHARA%20MITSUYASU&rft.date=2011-06-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2011129563A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true