TIMING VERIFICATION DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT, TIMING VERIFICATION METHOD, AND TIMING VERIFICATION PROGRAM

PROBLEM TO BE SOLVED: To perform timing verification in a short time with a smaller margin for environmental conditions. SOLUTION: A timing verification device for a semiconductor integrated circuit includes a storage unit, a condition normalization unit, a characterization unit, a representative value calculation unit, a determination coefficient calculation unit and a determination unit, wherein the storage unit holds environmental corner conditions for stipulating operation environment conditions for the semiconductor integrated circuit. The condition normalization unit performs normalization based on a maximum value and minimum value of the environmental corner conditions, and stores the normalized normalization environmental corner conditions in the storage unit. The characterization unit characterizes a delay library based on the normalization environmental corner conditions. The representative value calculation unit calculates a representative value of slack representing a timing margin in a circuit path by inputting circuit data for the semiconductor integrated circuit and performing timing analysis based on the characterized delay library. The determination coefficient calculation unit calculates a determination coefficient based on the normalization environmental corner conditions. The determination unit determines the timing by comparing the representative value with the determination coefficient. COPYRIGHT: (C)2011,JPO&INPIT