HETERO JUNCTION FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide a hetero junction field-effect transistor that suppresses current collapse and reduces a gate leakage current, and to provide a method of manufacturing the same. SOLUTION: The hetero junction field-effect transistor is formed of a nitride semiconductor, and includes...

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Bibliographische Detailangaben
Hauptverfasser: SHIOZAWA KATSUOMI, IMAI AKIFUMI, FUKITA MUNEYOSHI, ABE YUJI, NANJO TAKUMA, YAGYU EIJI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a hetero junction field-effect transistor that suppresses current collapse and reduces a gate leakage current, and to provide a method of manufacturing the same. SOLUTION: The hetero junction field-effect transistor is formed of a nitride semiconductor, and includes a semiconductor layer, and a gate electrode 90 arranged on the semiconductor layer so that a lower part is buried in the semiconductor layer. The semiconductor layer includes a barrier layer 40, and a cap layer 50 formed on the barrier layer 40 and having a thickness of ≤28 nm. COPYRIGHT: (C)2011,JPO&INPIT