SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To increase a breakdown voltage, reduce a consumption current, and increase a speed of operation of an MOS transistor formed on an SOI substrate. SOLUTION: An N-type low-concentration drain region 3, a source region 5, a drain ohmic region 7, a P-type channel region 9, and an o...

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1. Verfasser: NEGORO TAKAAKI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To increase a breakdown voltage, reduce a consumption current, and increase a speed of operation of an MOS transistor formed on an SOI substrate. SOLUTION: An N-type low-concentration drain region 3, a source region 5, a drain ohmic region 7, a P-type channel region 9, and an ohmic channel region 11 are formed in a silicon layer 1c at a depth reaching an embedded oxide film 1b. The low-concentrated drain region 3 is formed of two low-concentrated drain layers 3a, 3b having N-type impurity concentration higher as it is arranged on a side closer to a surface. The channel region 9 is formed of two channel layers 9a, 9b having P-type impurity concentration lower as it is arranged on a side closer to the surface. A gate electrode 15 is arranged above the channel region 9 and part of the low-concentrated drain region 3 at intervals with the ohmic drain region 7 when viewed from above. COPYRIGHT: (C)2011,JPO&INPIT