CIRCUIT VERIFICATION METHOD

PROBLEM TO BE SOLVED: To provide a circuit verification method for determining whether the circuit is structured to prevent a propagation failure in a re-convergence signal of a receiving side, in which a plurality of signals are re-converged, in a data propagation between non-synchronized clocks. S...

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1. Verfasser: SASE TAKUYA
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a circuit verification method for determining whether the circuit is structured to prevent a propagation failure in a re-convergence signal of a receiving side, in which a plurality of signals are re-converged, in a data propagation between non-synchronized clocks. SOLUTION: The circuit verification method in a circuit verification device includes: a signal value calculation procedure for calculating a logical value of a re-convergence point due to difference in change timing for each combination of signal changes of a plurality of signals that are re-converged on one re-convergence signal; and a verification property creation procedure for creating a verification property for verifying the occurrence of a signal change within one clock cycle of a receiving side clock for the combination of signal changes in which the logical value of the re-convergence point is different according to difference in the change timing. COPYRIGHT: (C)2011,JPO&INPIT