SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To suppress characteristic deterioration of a transistor, which constitutes a logic gate.SOLUTION: The semiconductor integrated circuit 70 is provided with: a multiplexer 1; a signal generation circuit 2; a control circuit 3; m inverters INV1 to m columns, n 2-input NOR circuit...

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Hauptverfasser: HOJO TAKEHIKO, WADA MASAHARU
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To suppress characteristic deterioration of a transistor, which constitutes a logic gate.SOLUTION: The semiconductor integrated circuit 70 is provided with: a multiplexer 1; a signal generation circuit 2; a control circuit 3; m inverters INV1 to m columns, n 2-input NOR circuits NOR1 to n, and n 2 shift registers SR1 to n to be cascaded. The control circuit 3 generates a control signal Sct in a disabled state in normal operation where a clock signal is supplied, and generates a control signal Sct in an enabled state other than in normal operation where no clock signal is supplied. The multiplexer 1 receives the clock signal Sclk and a low frequency signal Ssg to be output from a signal generator 2. The multiplexer 1 supplies the clock signal Sclk to the inverters INV1 to m column when the control signal Sct is disabled, and supplies the low frequency signal Ssg to the inverters INV1 to m column when the control signal Sct is enabled.