BUILT-IN TEST CIRCUIT, INTEGRATED CIRCUIT DEVICE, METHOD OF INITIALIZATION TEST OF SYNCHRONOUS CIRCUIT HAVING SCAN FUNCTION, AND METHOD OF GENERATING TEST PATTERN DATA

PROBLEM TO BE SOLVED: To easily perform an initialization test of a scan FF circuit by a simple design flow without providing any dedicated pads. SOLUTION: A built-in test circuit 2 includes: a scan chain 14 to which a plurality of synchronous circuits 12 having scan functions that are utilized as s...

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Bibliographische Detailangaben
1. Verfasser: SUGASHIMA KENJI
Format: Patent
Sprache:eng
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