SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND METHOD OF TESTING THE SAME
PROBLEM TO BE SOLVED: To achieve a scanning test and a delay test including the connection test between a manufacturer provided circuit and a client designed circuit, targeting a semiconductor integrated circuit device installed with the manufacturer provided circuit which is provided to the client...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | PROBLEM TO BE SOLVED: To achieve a scanning test and a delay test including the connection test between a manufacturer provided circuit and a client designed circuit, targeting a semiconductor integrated circuit device installed with the manufacturer provided circuit which is provided to the client by the manufacturer of a semiconductor integrated circuit device and for which the internal circuit information is undisclosed, and the client designed circuit which is designed by the client. SOLUTION: A wrapper circuit 13 is provided. An output delay test of an IP macro 12 is conducted by performing a delay test between the scan flip-flop 21, 22. An input delay test of the client designed circuit 14 is conducted by performing a delay test between the scan flip-flop 21, 24. If the IP macro 12 and the client designed circuit 14 pass the output delay test and the input delay test, respectively, it is determined that the delay between the scan flip-flop 21, 24 is within one cycle by a function clock F_CLK and the delay between the scan flip-flop 21, 24 is not a problem. COPYRIGHT: (C)2010,JPO&INPIT |
---|